DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/01/2023
Public

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14.2.4. AXI4-Stream Blocks (AXI4StreamReceiver and AXI4StreamTransmitter)

These blocks implement the AXI4-Stream receiver and transmitter interfaces as defined by the AMBA AXI-Stream Protocol Specification Issue B.

An AXI4StreamReceiver block at the front end of a system generates the appropriate hw.tcl code for an AXI4-Stream interface with the same name as the name of this block. An AXI4StreamTransmitter block at the back end of a system generates the appropriate hw.tcl code for an AXI4-Stream interface with same name as the name of this block.

You place the AXI4StreamReceiver and AXI4StreamTransmitter blocks either side of a DSP Builder subsystem. This arrangement allows you to design the DSP Builder subsystem in the middle without requiring any logic in the DSP Builder subsystem to handle backpressure (TREADY).

Figure 106. Typical AXI4-Stream Blocks System

When tx_tready is deasserted, the transmitter block immediately backpressures the receiver block via output_ready signal. The receiver block then latches the current input values and deasserts the rx_tready in the next cycle. The input_valid of the receiver is also immediately deasserted. No new valid data enters the DSP Builder subsystem in the middle. Any valid data already in the DSP Builder subsystem continues to the FIFO buffers in the transmitter block. You must appropriately size these FIFO buffers to ensure sufficient buffering capacity.

Many of the AXI4-Stream signals are optional. Drive any used inputs to their default values as specified by the AXI specification and connect any unused outputs to Simulink terminator blocks.

You may also remove the FIFO buffers associated with unused signals to reduce resource usage. AXI4-Stream blocks are Simulink masked subsystem. You may look under the mask to see their implementation.

The demo_axi4_stream.mdl example design demonstrates the AXI4-Stream blocks.

Table 90.  Port Interface for AXI4StreamReceiverThe signals with prefix rx implement the receiver interface. The signals with input prefix are usually connected to another DSP Builder subsystem.
Signal Direction Description
rx_tvalid Input

TVALID signal of the AXI4-Stream interface.

rx_tdata Input TDATA signal of the AXI4-Stream interface.
rx_tlast Input TLAST signal of the AXI4-Stream interface.
rx_tid Input TID signal of the AXI4-Stream interface.
rx_tdest Input TDEST signal of the AXI4-Stream interface.
rx_tuser Input TUSER signal of the AXI4-Stream interface.
rx_tkeep Input TKEEP signal of the AXI4-Stream interface.
rx_tstrb Input TSTRB signal of the AXI4-Stream interface.
rx_tready Output TREADY signal of the AXI4-Stream interface.
input_tvalid Output

This signal corresponds to the TVALID signal.

Usually connect to a DSP Builder subsystem.

input_tdata Output

This signal corresponds to the TDATA signal.

Usually connect to a DSP Builder subsystem.

input_tlast Output

This signal corresponds to the TLAST signal.

Usually connect to a DSP Builder subsystem.

input_tid Output

This signal corresponds to the TID signal.

Usually connect to a DSP Builder subsystem.

input_tdest Output

This signal corresponds to the TDEST signal.

Usually connect to a DSP Builder subsystem.

input_tuser Output

This signal corresponds to the TUSER signal.

Usually connect to a DSP Builder subsystem.

input_tkeep Output

This signal corresponds to the TKEEP signal.

Usually connect to a DSP Builder subsystem.

input_tstrb Output

This signal corresponds to the TSTRB signal.

Usually connect to a DSP Builder subsystem.

input_tready Input

This signal corresponds to the TREADY signal.

Usually connect to output_tready of an AXI4StreamTransmitter.

Table 91.  Port Interface for AXI4StreamTransmitterThe signals with prefix tx implement the transmitter interface. The signals with output prefix are usually connected to another DSP Builder subsystem.
Signal Direction Description
tx_tvalid Output

TVALID signal of the AXI4-Stream interface.

tx_tdata Output TDATA signal of the AXI4-Stream interface.
tx_tlast Output TLAST signal of the AXI4-Stream interface.
tx_tid Output TID signal of the AXI4-Stream interface.
tx_tdest Output TDEST signal of the AXI4-Stream interface.
tx_tuser Output TUSER signal of the AXI4-Stream interface.
tx_tkeep Output TKEEP signal of the AXI4-Stream interface.
tx_tstrb Output TSTRB signal of the AXI4-Stream interface.
tx_tready Input TREADY signal of the AXI4-Stream interface.
output_tvalid Input

This signal corresponds to the TVALID signal.

Usually connect to a DSP Builder subsystem.

output_tdata Input

This signal corresponds to the TDATA signal.

Usually connect to a DSP Builder subsystem.

output_tlast Input

This signal corresponds to the TLAST signal.

Usually connect to a DSP Builder subsystem.

output_tid Input

This signal corresponds to the TID signal.

Usually connect to a DSP Builder subsystem.

output_tdest Input

This signal corresponds to the TDEST signal.

Usually connect to a DSP Builder subsystem.

output_tuser Input

This signal corresponds to the TUSER signal.

Usually connect to a DSP Builder subsystem.

output_tkeep Input

This signal corresponds to the TKEEP signal.

Usually connect to a DSP Builder subsystem.

output_tstrb Input

This signal corresponds to the TSTRB signal.

Usually connect to a DSP Builder subsystem.

output_tready Output

This signal corresponds to the TREADY signal.

Usually connect to input_tready of an AXI4StreamReciever.

Table 92.  Parameters for AXI4StreamTransmitter Block
Parameter Description
FIFO Setup

Specify the size of the FIFO buffers in the AXI4-Stream Transmitter as a MATLAB vector of three elements:

[<_depth> <_fill_threshold> <_full_period>]

The AXI4-Stream Transmitter has FIFO buffers. You must appropriately set their size. Typical use cases have a DSP Builder subsystem between an AXI4-Stream Receiver and a Transmitter. When the FIFO buffers reach the full_period the transmitter deasserts output_tready. The output_tready is normally connected to an input_tready of a receiver. In response to input_tready, the receiver, deasserts rx_tready and prevents any new data from entering the system from outside. The FIFO buffers must have sufficient space (depth – full_period) to store the data already in the pipeline of the DSP Builder subsystem in the middle. The space must be greater than the latency of the DSP Builder subsystem or subsystems in the middle. _fill_threshold controls the empty output signals of the FIFO buffers that the AXI4-Stream transmitter does not use.