DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/01/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

12.2.1. DSP Builder Memory and Multiplier Trade-Off Options

When your design synthesizes to logic, DSP Builder creates delay blocks, whether explicitly from primitive delays, or in the IP library blocks. DSP Builder tries to balance the implementation between logic elements (LEs) and block memories (M9K, M20K, M20K, or M144K). The trade-off depends on the target FPGA family, but as a guideline the default trade-off is set to minimize the absolute silicon area the design uses. You can influence this trade-off.

DSP Builder converts multipliers with a single constant input into balanced adder trees, which occurs automatically where the depth of the tree is not greater than 2. If the depth is greater than 2, DSP Builder compares the hard multiplier threshold with the estimated size of the adder tree, which is generally much lower than the size of a full soft multiplier. If DSP Builder combines two non-constant multipliers followed by an adder into a single DSP block, DSP Builder does not convert the multiplier into LEs, even if a large threshold is present.