DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook
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7.4.12. Interpolating FIR Filter
The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks, plus ChanView block that deserialize the output buses. An Edit Params block allows easy access to the setup variables in the setup_demo_firi.m script.
The FilterSystem subsystem includes the Device and InterpolatingFIR blocks.
The model file is demo_firi.mdl.