7.14.1. 1-Antenna WiMAX DDC
The top-level testbench includes Control, Signals, and Run Quartus Prime blocks. the design includes an Edit Params block to allow easy access to the setup variables in the setup_wimax_ddc_1rx.m script.
The DDCChip subsystem includes Device, Decimating FIR, Mixer, NCO, SingleRateFIR, and Scale blocks. Also, an Interleaver subsystem extracts the correct I and Q channel data from the demodulated data stream.
The FIR filters implement a decimating filter chain that down convert the two channels from a frequency of 89.6 MSPS to a frequency of 11.2 MSPS (a total decimation rate of eight). The real mixer, NCO, and Interleaver subsystem isolate the two channels. The design configures the NCO with a single-channel to provide one sine and one cosine wave at a frequency of 22.4 MHz. The NCO has the same sample rate (89.6 MSPS) as the input data sample rate.
A system clock rate of 179.2 MHz drives the design on the FPGA that the Device block defines inside the DDCChip subsystem.
The model file is wimax_ddc_1rx.mdl.