15.3.5. Butterfly II C (BFIIC) (Deprecated)
You should parameterize this block with the incoming data type to ensure that DSP Builder maintains the necessary data precision. At the output, DSP Builder applies an additional bit of growth.
The s port connects to the control logic. This control logic is the extraction of the appropriate bit of a modulo N counter. The value of s determines the signal routing of each sample and the mathematical combination with other samples. The t port also connects to the control logic, but the extracted bit is different from the s port. The value of t determines whether an additional multiplication by –j occurs inside the butterfly unit.
|IFFT||Specifies that the design uses the BFIIC block in an IFFT.|
|Input bits||Specifies the number of input bits.|
|Input scaling exponent||Specifies the exponent part of the input scaling factor (2-exponent).|
|Allow output bitwidth growth||Specifies that the output is one bit wider than the input.|
|x1||Input||Complex fixed-point data-type determined by parameterization||Complex input from ComplexSampleDelay.|
|x2||Input||Complex fixed-point data-type determined by parameterization||Complex input from previous stage.|
|z1||Output||Derived complex fixed-point type||Complex output to next stage.|
|z2||Output||Derived complex fixed-point type||Complex output to ComplexSampleDelay.|