The NCO accumulates a phase angle in an accumulator. DSP Builder uses this angle as a lookup into sine and cosine tables to find a coarse sine and cosine approximation. DSP Builder implements the tables with a ROM. A Taylor series expansion of the small angle error refines this coarse approximation to produce accurate sine and cosine values. The NCO block uses folding to produce multiple sine and cosine values if the sample rate is an integer fraction of the system clock rate.
You can use this block in a digital up- or down-converter for a radio system or a general purpose DSP application. The coefficients and input data are fixed-point types, and the output is the implied full precision fixed-point type.
An NCO sometimes needs to synchronize its phase to an exact cycle. It uses the phase and sync inputs for this purpose. The sync input is a write enable for the channel (address) specified by the chan input when the new phase value (data) is available on the phase input. You may need some external logic (which you can implement as a primitive subsystem) to drive these signals. For example, you can prepare a sequence of new phase values in a shared memory and then write all the values to the NCO on a synchronization pulse. This option is particularly useful if you want an initial phase offset in the upper sinusoid.
The system specification, including such factors as the channel count, sample rates, and noise floor, determines the main parameters for this block. You can express all the parameters as MATLAB expressions, making it easy to parameterize a complete system.
The hardware generation techniques create very efficient NCOs, which are fast enough to update with every Simulink simulation. The edit-simulation loop time is much reduced, improving productivity.
|Output Rate Per Channel (MSPS)||The sine and cosine output rate per channel measured in millions of samples per second.|
|Output Data Type||The output width in bits of the NCO. The bit width controls the internal precision of the NCO. The spurious-free dynamic range (SFDR) of the waves produced is approximately 6.02 × bit width. The 6.02 factor comes from the definition of decibels with each added bit of precision increasing the SFDR by a factor of 20×log10(2).|
|Output Scaling Value||This value interprets the output data in the Simulink environment. The power of 2 scaling provided lets you specify the range of the output value.|
|Accumulator Bit Width||
Specifies the width of the memory-mapped accumulator bit width, which governs the NCO frequency accuracy that you can control. The width is limited to the range 15–30 for use with a 32-bit memory map (shared by other applications such as a Nios II processor). The top two bits in the 32-bit width are reserved to control the inversion of the sine and cosine outputs. Select Constant for the Read/Write Mode to increase the width to 40 bits.
Frequency resolution = clock frequency/2accumulator bit width
|Phase Increment and Inversion||A vector that represents the step in phase between each sample. This vector controls the frequencies generated during simulation. The length of the vector determines how many channels (frequencies) of data are generated from the NCO. The unit of the vector is one (sine or cosine) cycle.|
|Phase Increment and Inversion Memory Map||Specifies where in the memory-mapped space the NCO registers are mapped.|
|Read/Write Mode||Specifies whether the NCO phase increment and inversion registers are mapped as Read, Write, Read/Write, or Constant.|
|Expose Avalon Memory-Mapped Agent in Simulink||Allows you to reconfigure increments without Platform Designer. Also, it also allows you to reprogram multiple NCOs simultaneously. When you turn on this parameter, the following three additional input ports and two output ports appear in Simulink.