DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/01/2023
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15.6.17. Zero-Latency Latch (latch_0L)

The DSP Builder latch_0 block enable signal has an immediate effect on the output. While the enable is high, the data passes straight through. When the enable goes low, the latch_0 block outputs and holds the data input from the previous cycle.

The e signal is a ufix(1) enable signal. When e is high, the latch_0 block feeds data from input d through to output q. When e is low, the latch_0 block holds the last output.

A switch in e is effective immediately.