DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/01/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

13.2. Dependent Delay Library

Blocks from the DSP Builder advanced blockset Dependent Delay library implement delays outside of scheduled models, where the delay may depend on the latency of another model.

The ChannelDependentDelay block provides a sample delay on the connected signals. DSP Builder processes the signals similarly to a model that includes ChannelIn and ChannelOut blocks. DSP Builder identifies a specific valid and channel signal, then an arbitrary number of data lines.

The GPDependentDelay block is deprecated. Do not use this block in new designs.

The value of the sample delay may depend on the latency of referenced model, refer to the SynthesisInfo block.

Table 60.  Parameters for the ChannelDependentDelay Block
Parameter Description
Number of Data Signals

Specify the number of input and output (d and q) connections for the block.

DSP Builder passes each input to the corresponding output and delays it by the latency constraint.

Latency Constraint This option allows you to select the type of constraint and to specify its value. The value can be a workspace variable or an expression but must evaluate to a positive integer.

You can select the following types of constraint:

  • >: Greater than
  • >=: Greater than or equal to
  • =: Equal to
  • <=: Less than or equal to
  • <: Less than

Select either + or - and type in a reference model in the text field. Specify the reference as a Simulink path string e.g. ‘design/topLevel/model’. DSP Builder then ensures the latency depends on that model, otherwise the default is that DSP Builder depends on no model.

Local Reset-Minimization

Turn on to allow DSP Builder to apply reset minimization to the delays. You must also turn on Global Reset Minimization.

The values are:

  • Off. Default, no reset minimization.
  • On. DSP Builder applies no reset to all delay stages.
Table 61.  Port Interface for the ChannelDependentDelay Block
Parameter Direction Description
dv Input The input valid signal to delay.
qv Output The output for the valid signal.
dc Input The input channel number to delay.
qc Output The output for the channel.
d Input The input data to delay.
q Output The output for the corresponding to the input data.