DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/01/2023
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4.2.1. Verifying your DSP Builder Advanced Blockset Design with a Testbench

A DSP Builder design testbench is all the subsystems above the subsystem with the Device block. Many of the features of DSP Builder are more accessible if you develop the testbench flexibly.

Procedure

  1. Before you start implementing your algorithm, consider the modules that connect to and from your design. Understanding the interface to neighboring modules helps you to use the correct stimulus.
  2. Consider the sequence of events that you want to test.
  3. If multiple channels of data enter your design, align them properly to follow the DSP Builder advanced blockset data format.
  4. Plan your testbench, before you start your design, to allow you to verify and debug your implementation during the design phase.
  5. DSP Builder advanced blockset uses a standard interface protocol. Ensure every IP or customized block follows this protocol. The input and output signals of your hierarchical design have a common interface.
  6. Bring the output signals of subsystems to the top-level design.
  7. When you have the top-level testbench in place, debug your subsystems at all levels with the visualization features in Simulink and MATLAB.