DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/29/2022

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Give Feedback STATUS (0x50)

Table 240.  STATUS (0x50)
Name Bit(s) Access Description Reset
Reserved 31:12 - - -
Video locked 11 RO When asserted, indicates current signal value of the DisplayPort RX vid_lock signal. 0x0
Resolution valid 10 RO When asserted, indicates a valid resolution in the sample and line count registers. 0x0
Reserved 9 - - -
Stable 8 RO When asserted, the input video stream has had a consistent line length for two of the last three lines. 0x0
Interlaced 7 RO When asserted, the input video stream is interlaced. Otherwise, the input video stream is progressive. 0x0
Reserved 6:1 - - -
Status 0 RO This bit is asserted when the CV2AXI core is producing data. 0x0