DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/29/2022
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10.8.1. DPTX_AUX_CONTROL

For transaction requests:

  1. Wait for READY_TO_TX to be 1.
  2. Write registers DPTX_AUX_COMMAND to DPTX_AUX_BYTE18 with the transaction command, address, length (0 – 15) fields, and data payload.
  3. Write LENGTH with the transaction’s total message length (3 for header + 1 for length byte + 0 to 16 for data bytes).
  4. The request transmission begins.

For transaction replies:

  1. Issue a transaction request.
  2. Wait for MSG_READY to be 1. Implement a timeout.
  3. Read the transaction reply’s total length from LENGTH.
  4. Read the transaction reply's command from the DPTX_AUX_COMMAND register. This transaction clears MSG_READY and LENGTH.
  5. Read the transaction reply's data payload from registers DPTX_AUX_BYTE0 to DPTX_AUX_BYTE15 (read LENGTH - 1 bytes).

Address: 0x0100

Direction: RW

Reset: 0x00000000

Table 110.  DPTX_AUX_CONTROL Bits

Bit

Bit Name

Function

31

MSG_READY

0 = Waiting for a reply

1 = A reply has been completely received

30

READY_TO_TX

0 = Busy sending a request or waiting for a reply

1 = Ready to send a request

29:5

Unused

4:0

LENGTH

For the next transaction request, total length of message to be transmitted (3 – 20), for the last received transaction reply, total length of message received (1 – 17).