DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/29/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

11.9.25. DPRX_AUX_RESET

Address: 0x0118

Direction: WO

Reset: 0x00000000

Table 224.  DPRX_AUX_RESET Bits

Bit

Bit Name

Function

31:1

Unused

0

CL EA R

Asserting CLEAR resets the AUX controller state machine:

  • 0 = No action
  • 1 = AUX Controller reset