DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/29/2022
Public

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10.10.2.1. STATUS (0x50)

Table 134.  STATUS (0x50)
Name Bit(s) Access Description Reset
Reserved 31:1 - - -
Status 0 RO When asserted, the AXI2CV is producing data. 0x0