DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/29/2022
Public

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11.3.1. DPRX_BER_CNTI0

Internal bit-error counters for lane 0 and lane 1.

Address: 0x0006

Direction: RO

Reset: 0x00000000

Table 162.  DPRX_BER_CNTI0 Bits

Bit

Bit Name

Function

31

Unused

30:16

CNT1

Symbol error counter for lane 1

15

Unused

14:0

CNT0

Symbol error counter for lane 0

These registers are meant for internal use and are not exposed in the DPCD.