DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/29/2022
Public

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Document Table of Contents

10.3.14. DPTX_TEST_264BIT_PATTERN9

Address: 0x001D

Direction: RW

Reset: 0x00000000

Table 94.  DPTX_TEST_264BIT_PATTERN9 Bits

Bit

Bit Name

Function

31:8

Reserved

7:0

264BIT_PATTERN9

Bits 263:256 of the 264 bit custom pattern for PHY compliance test.