DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/29/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

10.2.16. DPTX0_VBID

Address: 0x002f

Direction: RO

Reset: 0x00000000

Table 80.  DPTX0_VBID Bits

Bit

Bit Name

Function

31:8

Unused

 

7

MSA_LOCK

0 = Input video timing unstable

1 = Input video timing stable

6:5

Unused  

4:0

VBID[4:0]

VB-ID flags (refer to the VESA DisplayPort Standard).