DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/29/2022
Public

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11.1.2. DPRX_RX_STATUS

GXB_BUSY connects to the rx_reconfig_busy input port.

Address: 0x0001

Direction: CRO

Reset: 0x00000000

Table 157.  DPRX_RX_STATUS Bits

Bit

Bit Name

Function

31:21

Unused

20

FEC_RUNNING_INDICATOR

8B/10B Channel Coding:

Reserved

128B/132B Channel Coding:

0 = FEC is not running

1 = FEC is running

19

FEC_DECODE_DIS_DETECTED

8B/10B Channel Coding:

Reserved

128B/132B Channel Coding:

0 = FEC_DECODE_DIS control link symbol not detected

1 = FEC_DECODE_DIS control link symbol detected

18

FEC_DECODE_EN_DETECTED

8B/10B Channel Coding:

Reserved

128B/132B Channel Coding:

0 = FEC_DECODE_EN control link symbol not detected

1 = FEC_DECODE_EN control link symbol detected

17

GXB_BUSY

0 = Transceiver not busy

1 = Transceiver busy

16

SYNC_LOSS

This flag can be reset by writing it to 1:

0 = Symbol lock on all lanes in use

1 = Symbol lock lost on one or more of the used lanes

15:9

Unused

8 INTERLANE_ALIGN

0 = Inter-lane alignment not achieved

1 = Inter-lane alignment achieved

7

SYM_LOCK3

0 = Symbol unlocked (lane 3)

1 = Symbol locked (lane 3)

6

SYM_LOCK2

0 = Symbol unlocked (lane 2)

1 = Symbol locked (lane 2)

5

SYM_LOCK1

0 = Symbol unlocked (lane 1)

1 = Symbol locked (lane 1)

4

SYM_LOCK0

0 = Symbol unlocked (lane 0)

1 = Symbol locked (lane 0)

3

CR_LOCK3

0 = Clock unlocked (lane 3)

1 = Clock locked (lane 3)

2

CR_LOCK2

0 = Clock unlocked (lane 2)

1 = Clock locked (lane 2)

1

CR_LOCK1

0 = Clock unlocked (lane 1)

1 = Clock locked (lane 1)

0

CR_LOCK0

0 = Clock unlocked (lane 0)

1 = Clock locked (lane 0)