DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/29/2022
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11.1.4. DPRX_BER_CNT0

These registers are exposed in DPCD locations SYMBOL_ERROR_COUNT_LANE0 and SYMBOL_ERROR_COUNT_LANE1.

Address: 0x0003

Direction: RO

Reset: 0x00000000

Table 159.  DPRX_RX_STATUS Bits

Bit

Bit Name

Function

31

Unused

30:16

CNT1 Symbol error counter for lane 1

15

Unused

14:0

CNT0 Symbol error counter for lane 0