DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/29/2022
Public

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11. DisplayPort Sink Register Map and DPCD Locations

DisplayPort sink instantiations greatly benefit from and may optionally use an embedded controller (Nios II processor or another controller). This section describes the register map.

Table 155.  Notation

Shorthand

Definition

RW

Read/write

RO

Read only

WO

Write only

CRO

Clear on read or write, read only

CWO

Clear on read or write, write only