DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/29/2022
Public

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6.4. HDCP 1.3 RX Architecture

The HDCP 1.3 receiver block decrypts the protected video and secondary data, including main stream attributes (MSA), from the connected HDCP 1.3 device. The HDCP 1.3 receiver block has identical structure layers as the HDCP 1.3 transmitter block.
Figure 32. Architecture Block Diagram of HDCP 1.3 RX IP

The HDCP 1.3 RX core is fully autonomous. For DisplayPort application, the HDCP transmitter and the HDCP receiver communicates the HDCP register values over the AUX channel. Turn on the Enable GPU control parameter and use a Nios® II processor to drive the HDCP 1.3 RX core through the HDCP Register Port ( Avalon® memory-mapped interface). The HDCP Register Port is not exposed and will be automatically driven when you enable the Support HDCP 1.3 parameter.

The HDCP specifications requires the HDCP 1.3 RX core to be programmed with the DCP-issued production key – Device Private Keys (Bkeys) and Key Selection Vector (Bksv). The IP retrieves the key from the on-chip memory externally to the core through the HDCP Key Port (rx_hdcp interface). The on-chip memory must store the key data in the arrangement shown in the table below.

Table 37.  HDCP 1.3 RX Key Port Addressing
Address Content
6'h28 {16’d0, Bksv[39:0]}
6'h27 Bkeys39[55:0]
6'h26 Bkeys38[55:0]
... ...
6'h01 Bkeys01[55:0]
6'h00 Bkeys00[55:0]

The Video Stream and Secondary Data Layer receives audio and video content over its Video and Secondary Data Input Port, and performs the decryption operation. The Video Stream and Secondary Data Layer detects the Encryption Status Signaling (ESS) provided by the DisplayPort IP to determine when to decrypt frames.

To implement the HDCP 1.3 RX core as a repeater upstream interface, the IP must propagate certain information such as KSV list and Bstatus to the upstream transmitter and to be used for SHA-1 hash digest. The repeater downstream interface (TX) must provide this information through the Repeater Message Port (rx_rpt_msg interface) using the Avalon® memory-mapped interface. You can use the same clock source to drive the clocking for the HDCP Register Port (or the controller interface of the DisplayPort Intel® FPGA IP) and Repeater Message Port.

The mapping for the RX registers defined in the following table is equivalent to the address space for HDCP 1.3 receiver defined in the HDCP specification.

Table 38.  HDCP 1.3 RX Register Mapping
Address Register R/W Reset Bit Bit Name Description
0x00 BKSV0 RO 7:0 Bit [7:0] of HDCP Receiver KSV.
0x01 BKSV1 7:0 Bit [15:8] of HDCP Receiver KSV.
0x02 BKSV2 7:0 Bit [23:16] of HDCP Receiver KSV.
0x03 BKSV3 7:0 Bit [31:24] of HDCP Receiver KSV.
0x04 BKSV4 7:0 Bit [39:32] of HDCP Receiver KSV.
0x05 RO_PRIME0 RO 0x00 7:0 Authentication response. Bit [7:0] of RO’.
0x06 RO_PRIME1 7:0 Authentication response. Bit [15:8] of RO’.
0x07 AKSV0 WO 0x00 7:0 Bit [7:0] of HDCP Transmitter KSV.
0x08 AKSV1 7:0 Bit [15:8] of HDCP Transmitter KSV.
0x09 AKSV2 7:0 Bit [23:16] of HDCP Transmitter KSV.
0x0A AKSV3 7:0 Bit [31:24] of HDCP Transmitter KSV.
0x0B AKSV4 7:0 Bit [39:32] of HDCP Transmitter KSV.
0x0C AN0 WO 0x00 7:0 Bit [7:0] of HDCP Session Random Number An.
0x0D AN1 7:0 Bit [15:8] of HDCP Session Random Number An.
0x0E AN2 7:0 Bit [23:16] of HDCP Session Random Number An.
0x0F AN3 7:0 Bit [31:24] of HDCP Session Random Number An.
0x10 AN4 7:0 Bit [39:32] of HDCP Session Random Number An.
0x11 AN5 7:0 Bit [47:40] of HDCP Session Random Number An.
0x12 AN6 7:0 Bit [55:48] of HDCP Session Random Number An.
0x13 AN7 7:0 Bit [63:56] of HDCP Session Random Number An.
0x14 V_PRIME_H0_0 RO 0x00 7:0 H0 part of SHA-1 hash value used in the authentication protocol HDCP repeaters. Bit [7:0] of H0 value.
0x15 V_PRIME_H0_1 7:0 Bit [15:8] of H0 value.
0x16 V_PRIME_H0_2 7:0 Bit [23:16] of H0 value.
0x17 V_PRIME_H0_3 7:0 Bit [31:24] of H0 value.
0x18 V_PRIME_H1_0 RO 0x00 7:0 H1 part of SHA-1 hash value used in the authentication protocol HDCP repeaters. Bit [7:0] of H1 value.
0x19 V_PRIME_H1_1 7:0 Bit [15:8] of H1 value.
0x1A V_PRIME_H1_2 7:0 Bit [23:16] of H1 value.
0x1B V_PRIME_H1_3 7:0 Bit [31:24] of H1 value.
0x1C V_PRIME_H2_0 RO 0x00 7:0 H2 part of SHA-1 hash value used in the authentication protocol HDCP repeaters. Bit [7:0] of H2 value.
0x1D V_PRIME_H2_1 7:0 Bit [15:8] of H2 value.
0x1E V_PRIME_H2_2 7:0 Bit [23:16] of H2 value.
0x1F V_PRIME_H2_3 7:0 Bit [31:24] of H2 value.
0x20 V_PRIME_H3_0 RO 0x00 7:0 H3 part of SHA-1 hash value used in the authentication protocol HDCP repeaters. Bit [7:0] of H3 value.
0x21 V_PRIME_H3_1 7:0 Bit [15:8] of H3 value.
0x22 V_PRIME_H3_2 7:0 Bit [23:16] of H3 value.
0x23 V_PRIME_H3_3 7:0 Bit [31:24] of H3 value.
0x24 V_PRIME_H4_0 RO 0x00 7:0 H4 part of SHA-1 hash value used in the authentication protocol HDCP repeaters. Bit [7:0] of H4 value.
0x25 V_PRIME_H4_1 7:0 Bit [15:8] of H4 value.
0x26 V_PRIME_H4_2 7:0 Bit [23:16] of H4 value.
0x27 V_PRIME_H4_3 7:0 Bit [31:24] of H4 value.
0x28 BCAPS RO 0x000 7:2 Reserved

These bits read as 0.

1 REPEATER

HDCP repeater capability.

0 = Receiver is not a repeater.

1 = Receiver is a repeater.

0 HDCP_CAPABLE This bit reads as 1.
0x29 BSTATUS RO 0x00 7:4 Reserved These bits read as 0.
3 REAUTHENTICATION_REQUEST Refer to HDCP on DisplayPort specification version 1.3 for more information.
2 LINK_INTEGRITY_FAILURE
1 RO'_AVAILABLE
0 READY
0x2A BINFO0 RO 0x00 7 MAX_DEVS_EXCEEDED Topology error indicator. When set to 1, more than 127 downstream devices are attached.
6:0 DEVICE_COUNT Total number of attached downstream devices. Always zero for HDCP receivers. This count does not include the HDCP repeater itself, but only the downstream devices from the HDCP repeater.
0x2B BINFO1 RO 0x00 7:4 Reserved These bits read as 0.
3 MAX_CASCADE_EXCEEDED Topology error indicator. When set to 1, more than 7 levels of video repeater are cascaded together.
2:0 DEPTH 3-bit repeater cascade depth. This value gives the number of attached levels throughout the connection topology.
0x2C KSV_FIFO RO 0x00 7:0 Key selection vector FIFO. Used to pull downstream KSVs from HDCP repeaters using auto-incrementing address. All bytes read as 0x00 for HDCP receivers that are not HDCP repeaters (REPEATER=0).
0x3E CTRL WO 0x00 31 Reserved Reserved.
30 CP_IRQ_DET Set to 1 to reset the CP_IRQ_STATUS flag in the STATUS register.
29 KSV_FIFO_OFFSET_RST Set to 1 to reset the offset of the KSV_FIFO register.
28 EXIT_AUTH Exit authenticated state.
27:0 Reserved Reserved.
0x3F STATUS RO 0x00 31:20 Reserved Reserved.
19 AUTHENTICATED

0: HDCP 1.3x event is in authenticated state.

1: HDCP 1.3x event is in unauthenticated state.

18 CP_IRQ_STATUS

0: No HDCP 1.3 event.

1: An HDCP 1.3 event occurred and HPD interrupts were generated.

17:0 Reserved Reserved.
Table 39.  HDCP 1.3 RX Repeater Register Mapping
Address Register R/W Reset Bit Bit Name Description
0x00 RPT_KSV_LIST WO 0x00000000 31:8 Reserved Reserved
7:0 KSV_LIST Byte write KSV List in big endian order.
0x01 RPT_BSTATUS RW 0x00000000 31:19 Reserved Reserved
18 REQUEST Read-only. Asserted by the core to request for KSV_LIST and BSTATUS. This usually happens when re-authentication is triggered by the connected upstream. Note that when REQUEST is asserted, the READY should also be asserted.
17 READY Read-only. Asserted by the core to indicate KSV_LIST and BSTATUS are processed. Write KSV_LIST and BSTATUS after this bit is asserted.
16 VALID Set to 1 after KSV_LIST and BSTATUS are written. Self-cleared by the core after KSV_LIST and BSTATUS are read.
15:0 BSTATUS

[15:12]: Reserved.

[11]: MAX_CASCADE_EXCEEDED

[10:8]: DEPTH

[7]: MAX_DEVS_EXCEEDED

[6:0]: DEVICE_COUNT

0x02 RPT_MISC RW 31:1 Reserved Reserved.
0 REPEATER

Set to 0 if no downstream is connected or if the connected downstream is not HDCP 1.3-capable. This means the receiver IP is an end-point receiver rather than a repeater.

Set to 1 if the connected downstream is HDCP-capable.