DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/29/2022
Public

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5.2.4.1. DP1.4 (8B/10B Channel Coding)

The IP multiplexes the packetized data, MSA data, and blank generator data into a single stream.

The combined data goes through a scrambler and an 8B/10B encoder, and is available as a 20-bit double-rate or a 40-bit quad-rate DisplayPort encoded video port. The 20- or 40-bit port connects directly to the Intel FPGA high-speed output transceiver.

During training periods, the source can send the DisplayPort clock recovery and symbol lock test patterns (training pattern 1, training pattern 2, and training pattern 3, respectively), upon receiving the request from downstream DisplayPort sink.

The DisplayPort source also supports a test procedure for measuring the link quality, including these features:
  • Transmission of a Nyquist pattern (repetition of D10.2 symbols without scrambling)
  • Symbol Error measurement pattern
  • PRBS7 bit pattern
  • Custom 80-bit repeating pattern
  • HBR2 Compliance EYE pattern

Only the Symbol Error measurement pattern and HBR2 Compliance EYE pattern require both scrambling and 8B/10B encoding. The PBRS7 pattern and Custom 80-bit pattern do not require scrambling or 8B/10B encoding. Training patterns 1, 2, and 3, and D10.2 test pattern require only 8B/10B encoding.