DisplayPort Intel® FPGA IP User Guide

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ID 683273
Date 4/29/2022
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Quick Reference 2. About This IP 3. Getting Started 4. DisplayPort Intel® FPGA IP Hardware Design Examples 5. DisplayPort Source 6. DisplayPort Sink 7. DisplayPort Intel® FPGA IP Parameters 8. DisplayPort Intel® FPGA IP Simulation Example 9. DisplayPort API Reference 10. DisplayPort Source Register Map and DPCD Locations 11. DisplayPort Sink Register Map and DPCD Locations 12. DisplayPort Intel® FPGA IP User Guide Archives 13. Document Revision History for the DisplayPort Intel® FPGA IP User Guide
1. DisplayPort Intel® FPGA IP Quick Reference x
1.1. DisplayPort Terms and Acronyms
2. About This IP x
2.1. Release Information 2.2. Device Family Support 2.3. IP Core Verification 2.4. Performance and Resource Utilization
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying IP Parameters and Options 3.3. Simulating the Design 3.4. Compiling the Full Design and Programming the FPGA 3.5. Calculating Video Bandwidth and Recovered Pixel Clock Frequency
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.3. Simulating the Design x
3.3.1. Simulating with the ModelSim Simulator
4. DisplayPort Intel® FPGA IP Hardware Design Examples x
4.1. DisplayPort Intel® FPGA IP Hardware Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-Tile Devices 4.2. HDCP Over DisplayPort Design Example for Intel® Arria® 10 and Intel® Stratix® 10 Devices 4.3. DisplayPort Intel® FPGA IP Hardware Design Examples for Arria V, Cyclone V, and Stratix V Devices
4.3. DisplayPort Intel® FPGA IP Hardware Design Examples for Arria V, Cyclone V, and Stratix V Devices x
4.3.1. Clock Recovery Core 4.3.2. Transceiver and Clocking 4.3.3. Required Hardware 4.3.4. Design Walkthrough 4.3.5. DisplayPort Link Training Flow 4.3.6. DisplayPort Post Link Training Adjust Request Flow (LQA) 4.3.7. DisplayPort MST Source User Application
4.3.1. Clock Recovery Core x
4.3.1.1. Clock Recovery Core Parameters 4.3.1.2. Clock Recovery Interface
4.3.1.2. Clock Recovery Interface x
4.3.1.2.1. Video Input Port
4.3.4. Design Walkthrough x
4.3.4.1. Set Up the Hardware 4.3.4.2. Copy the Design Files to Your Working Directory 4.3.4.3. Build the FPGA Design 4.3.4.4. Load and Run the Software 4.3.4.5. View the Results
5. DisplayPort Source x
5.1. IP to Transceiver Parallel Data Interface Width 5.2. Main Data Path 5.3. Controller Interface 5.4. Sideband Channel 5.5. Source Embedded DisplayPort (eDP) Support 5.6. HDCP 1.3 TX Architecture 5.7. HDCP 2.3 TX Architecture 5.8. Source Interfaces 5.9. Source Clock Tree
5.2. Main Data Path x
5.2.1. Video Packetizer Path 5.2.2. Video Geometry Measurement Path 5.2.3. Audio and Secondary Stream Encoder Path 5.2.4. Training and Link Quality Patterns Generator
5.2.4. Training and Link Quality Patterns Generator x
5.2.4.1. DP1.4 (8B/10B Channel Coding) 5.2.4.2. DP2.0 (128B/132B Channel Coding)
5.8. Source Interfaces x
5.8.1. Controller Interface 5.8.2. AUX Interface 5.8.3. Video Interface 5.8.4. TX Transceiver Interface 5.8.5. Transceiver Reconfiguration Interface 5.8.6. Transceiver Analog Reconfiguration Interface 5.8.7. Secondary Stream Interface 5.8.8. Audio Interface
5.8.3. Video Interface x
5.8.3.1. Video Interface (TX Video IM Enable = 0) 5.8.3.2. Video Interface (TX Video IM Enable = 1) 5.8.3.3. Video Interface (Enable Active Video Data Protocols = AXIS-VVP Full)
6. DisplayPort Sink x
6.1. Transceiver to IP Parallel Data Interface Width 6.2. Sink Embedded DisplayPort (eDP) Support 6.3. Sink Non-GPU Mode Support 6.4. HDCP 1.3 RX Architecture 6.5. HDCP 2.3 RX Architecture 6.6. Sink Interfaces 6.7. Sink Clock Tree
6.6. Sink Interfaces x
6.6.1. Controller Interface 6.6.2. AUX Interface 6.6.3. Debugging Interface 6.6.4. Video Interface 6.6.5. Video Interface (Enable Active Video Data Protocols = AXIS-VVP Full) 6.6.6. Clocked Video Input Interface 6.6.7. RX Transceiver Interface 6.6.8. Transceiver Reconfiguration Interface 6.6.9. Secondary Stream Interface 6.6.10. Audio Interface 6.6.11. Non-GPU Mode EDID Interface 6.6.12. MSA Interface
6.6.2. AUX Interface x
6.6.2.1. AUX Debug Interface 6.6.2.2. EDID Interface
6.6.3. Debugging Interface x
6.6.3.1. Link Parameters Interface 6.6.3.2. Video Stream Out Interface
7. DisplayPort Intel® FPGA IP Parameters x
7.1. DisplayPort Intel® FPGA IP Source Parameters 7.2. DisplayPort Intel® FPGA IP Sink Parameters
8. DisplayPort Intel® FPGA IP Simulation Example x
8.1. Design Walkthrough
8.1. Design Walkthrough x
8.1.1. Copy the Simulation Files to Your Working Directory 8.1.2. Generate the IP Simulation Files and Scripts, and Compile and Simulate 8.1.3. View the Results
9. DisplayPort API Reference x
9.1. Using the Library 9.2. btc_dprx_syslib API Reference 9.3. btc_dprx_aux_get_request 9.4. btc_dprx_aux_handler 9.5. btc_dprx_aux_post_reply 9.6. btc_dprx_baseaddr 9.7. btc_dprx_dpcd_gpu_access 9.8. btc_dprx_edid_set 9.9. btc_dprx_hpd_get 9.10. btc_dprx_hpd_pulse 9.11. btc_dprx_hpd_set 9.12. btc_dprx_lt_eyeq_init 9.13. btc_dprx_lt_force 9.14. btc_dprx_rtl_ver 9.15. btc_dprx_sw_ver 9.16. btc_dprx_syslib_add_rx 9.17. btc_dprx_syslib_info 9.18. btc_dprx_syslib_init 9.19. btc_dprx_syslib_monitor 9.20. btc_dprx_mst_link_addr_rep_set 9.21. btc_dprx_mst_conn_stat_notify_req 9.22. btc_dprx_mst_conn_stat_notify_rep 9.23. btc_dptx_syslib API Reference 9.24. btc_dptx_aux_i2c_read 9.25. btc_dptx_aux_i2c_write 9.26. btc_dptx_aux_read 9.27. btc_dptx_aux_write 9.28. btc_dptx_baseaddr 9.29. btc_dptx_edid_block_read 9.30. btc_dptx_edid_read 9.31. btc_dptx_fast_link_training 9.32. btc_dptx_hpd_change 9.33. btc_dptx_is_link_up 9.34. btc_dptx_link_bw 9.35. btc_dptx_link_training 9.36. btc_dptx_rtl_ver 9.37. btc_dptx_set_color_space 9.38. btc_dptx_sw_ver 9.39. btc_dptx_syslib_add_tx 9.40. btc_dptx_syslib_init 9.41. btc_dptx_syslib_monitor 9.42. btc_dptx_test_autom 9.43. btc_dptx_video_enable 9.44. btc_dptx_mst_allocate_payload_rep 9.45. btc_dptx_mst_allocate_payload_req 9.46. btc_dptx_mst_clear_payload_table_rep 9.47. btc_dptx_mst_clear_payload_table_req 9.48. btc_dptx_mst_conn_stat_notify_req 9.49. btc_dptx_mst_down_rep_irq 9.50. btc_dptx_mst_enable 9.51. btc_dptx_mst_enum_path_rep 9.52. btc_dptx_mst_enum_path_req 9.53. btc_dptx_mst_get_msg_transact_ver_rep 9.54. btc_dptx_mst_get_msg_transact_ver_req 9.55. btc_dptx_mst_link_address_rep 9.56. btc_dptx_mst_link_address_req 9.57. btc_dptx_mst_remote_dpcd_wr_rep 9.58. btc_dptx_mst_remote_dpcd_wr_req 9.59. btc_dptx_mst_remote_i2c_rd_rep 9.60. btc_dptx_mst_remote_i2c_rd_req 9.61. btc_dptx_mst_set_color_space 9.62. btc_dptx_mst_tavgts_set 9.63. btc_dptx_mst_up_req_irq 9.64. btc_dptx_mst_vcpid_set 9.65. btc_dptx_mst_vcptab_addvc 9.66. btc_dptx_mst_vcptab_clear 9.67. btc_dptx_mst_vcptab_delvc 9.68. btc_dptx_mst_vcptab_update 9.69. btc_dptxll_syslib API Reference 9.70. btc_dptxll_hpd_change 9.71. btc_dptxll_hpd_irq 9.72. btc_dptxll_mst_cmp_ports 9.73. btc_dptxll_mst_edid_read_rep 9.74. btc_dptxll_mst_edid_read_req 9.75. btc_dptxll_mst_get_device_ports 9.76. btc_dptxll_mst_set_csn_callback 9.77. btc_dptxll_mst_topology_discover 9.78. btc_dptxll_stream_allocate_rep 9.79. btc_dptxll_stream_allocate_req 9.80. btc_dptxll_stream_calc_VCP_size 9.81. btc_dptxll_stream_delete_rep 9.82. btc_dptxll_stream_delete_req 9.83. btc_dptxll_stream_get 9.84. btc_dptxll_stream_set_color_space 9.85. btc_dptxll_stream_set_pixel_rate 9.86. btc_dptxll_sw_ver 9.87. btc_dptxll_syslib_add_tx 9.88. btc_dptxll_syslib_init 9.89. btc_dptxll_syslib_monitor 9.90. btc_dpxx_syslib Additional Types 9.91. btc_dprx_syslib Supported DPCD Locations
10. DisplayPort Source Register Map and DPCD Locations x
10.1. Source General Registers 10.2. Source MSA Registers 10.3. Source Link PHY Control and Status 10.4. Source Timestamp 10.5. Source CRC Registers 10.6. Source Audio Registers 10.7. Source MST Registers 10.8. Source AUX Controller Interface 10.9. Source-Supported DPCD Locations 10.10. Source AXI2CV Registers
10.1. Source General Registers x
10.1.1. DPTX_TX_CONTROL 10.1.2. DPTX_TX_STATUS 10.1.3. DPTX_TX_VERSION
10.2. Source MSA Registers x
10.2.1. DPTX0_MSA_MVID 10.2.2. DPTX0_MSA_NVID 10.2.3. DPTX0_MSA_HTOTAL 10.2.4. DPTX0_MSA_VTOTAL 10.2.5. DPTX0_MSA_HSP 10.2.6. DPTX0_MSA_HSW 10.2.7. DPTX0_MSA_HSTART 10.2.8. DPTX0_MSA_VSTART 10.2.9. DPTX0_MSA_VSP 10.2.10. DPTX0_MSA_VSW 10.2.11. DPTX0_MSA_HWIDTH 10.2.12. DPTX0_MSA_VHEIGHT 10.2.13. DPTX0_MSA_MISC0 10.2.14. DPTX0_MSA_MISC1 10.2.15. DPTX0_MSA_COLOR 10.2.16. DPTX0_VBID
10.3. Source Link PHY Control and Status x
10.3.1. DPTX_PRE_VOLT0/DPTX_REG_TXFFE0 10.3.2. DPTX_PRE_VOLT1/DPTX_REG_TXFFE1 10.3.3. DPTX_PRE_VOLT2/DPTX_REG_TXFFE2 10.3.4. DPTX_PRE_VOLT3/DPTX_REG_TXFFE3 10.3.5. DPTX_RECONFIG 10.3.6. DPTX_TEST_80BIT_PATTERN1/DPTX_TEST_264BIT_PATTERN1 10.3.7. DPTX_TEST_80BIT_PATTERN2/DPTX_TEST_264BIT_PATTERN2 10.3.8. DPTX_TEST_80BIT_PATTERN3/DPTX_TEST_264BIT_PATTERN3 10.3.9. DPTX_TEST_264BIT_PATTERN4 10.3.10. DPTX_TEST_264BIT_PATTERN5 10.3.11. DPTX_TEST_264BIT_PATTERN6 10.3.12. DPTX_TEST_264BIT_PATTERN7 10.3.13. DPTX_TEST_264BIT_PATTERN8 10.3.14. DPTX_TEST_264BIT_PATTERN9
10.7. Source MST Registers x
10.7.1. DPTX_MST_VCPTAB0 10.7.2. DPTX_MST_VCPTAB1 10.7.3. DPTX_MST_VCPTAB2 10.7.4. DPTX_MST_VCPTAB3 10.7.5. DPTX_MST_VCPTAB4 10.7.6. DPTX_MST_VCPTAB5 10.7.7. DPTX_MST_VCPTAB6 10.7.8. DPTX_MST_VCPTAB7 10.7.9. DPTX_MST_TAVG_TS
10.8. Source AUX Controller Interface x
10.8.1. DPTX_AUX_CONTROL 10.8.2. DPTX_AUX_COMMAND 10.8.3. DPTX_AUX_BYTE0 10.8.4. DPTX_AUX_BYTE1 10.8.5. DPTX_AUX_BYTE2 10.8.6. DPTX_AUX_BYTE3 10.8.7. DPTX_AUX_BYTE4 10.8.8. DPTX_AUX_BYTE5 10.8.9. DPTX_AUX_BYTE6 10.8.10. DPTX_AUX_BYTE7 10.8.11. DPTX_AUX_BYTE8 10.8.12. DPTX_AUX_BYTE9 10.8.13. DPTX_AUX_BYTE10 10.8.14. DPTX_AUX_BYTE11 10.8.15. DPTX_AUX_BYTE12 10.8.16. DPTX_AUX_BYTE13 10.8.17. DPTX_AUX_BYTE14 10.8.18. DPTX_AUX_BYTE15 10.8.19. DPTX_AUX_BYTE16 10.8.20. DPTX_AUX_BYTE17 10.8.21. DPTX_AUX_BYTE18 10.8.22. DPTX_AUX_RESET
10.10. Source AXI2CV Registers x
10.10.1. Source AXI2CV Registers Summary 10.10.2. Source AXI2CV Registers Description
10.10.2. Source AXI2CV Registers Description x
10.10.2.1. STATUS (0x50) 10.10.2.2. VIDEO_MODE_MATCH (0X51) 10.10.2.3. VIDEO_MODE_BANK_SELECT (0x53) 10.10.2.4. VIDEO_MODE_CONTROL (0x54) 10.10.2.5. VIDEO_MODE_SAMPLE_COUNT(0x55) 10.10.2.6. VIDEO_MODE_F0_LINE_COUNT (0x56) 10.10.2.7. VIDEO_MODE_F1_LINE_COUNT (0x57) 10.10.2.8. VIDEO_MODE_HORIZONTAL_FRONT_PORCH (0x58) 10.10.2.9. VIDEO_MODE_HORIZONTAL_SYNC_LENGTH (0x59) 10.10.2.10. VIDEO_MODE_HORIZONTAL_BLANKING (0x5A) 10.10.2.11. VIDEO_MODE_VERTICAL_FRONT_PORCH (0x5B) 10.10.2.12. VIDEO_MODE_VERTICAL_SYNC_LENGTH (0x5C) 10.10.2.13. VIDEO_MODE_VERTICAL_BLANKING (0x5D) 10.10.2.14. VIDEO_MODE_F0_VERTICAL_FRONT_PORCH (0x5E) 10.10.2.15. VIDEO_MODE_F0_VERTICAL_SYNC_LENGTH (0x5F) 10.10.2.16. VIDEO_MODE_F0_VERTICAL_BLANKING (0x60) 10.10.2.17. VIDEO_MODE_ACTIVE_PICTURE_LINE (0x61) 10.10.2.18. VIDEO_MODE_F0_VERTICAL_RISING (0x62) 10.10.2.19. VIDEO_MODE_FIELD_RISING (0x63) 10.10.2.20. VIDEO_MODE_FIELD_FALLING (0x64) 10.10.2.21. VIDEO_MODE_VALID (0x6D)
11. DisplayPort Sink Register Map and DPCD Locations x
11.1. Sink General Registers 11.2. Sink Timestamp 11.3. Sink Bit-Error Counters 11.4. FEC Registers 11.5. 128B/132B Link Quality Test Pattern Registers 11.6. Sink MSA Registers 11.7. Sink Audio Registers 11.8. Sink MST Registers 11.9. Sink AUX Controller Interface 11.10. Sink CRC Registers 11.11. Sink-Supported DPCD Locations 11.12. Sink CV2AXI Registers
11.1. Sink General Registers x
11.1.1. DPRX_RX_CONTROL 11.1.2. DPRX_RX_STATUS 11.1.3. DPRX_BER_CONTROL 11.1.4. DPRX_BER_CNT0 11.1.5. DPRX_BER_CNT1
11.3. Sink Bit-Error Counters x
11.3.1. DPRX_BER_CNTI0 11.3.2. DPRX_BER_CNTI1
11.4. FEC Registers x
11.4.1. DPRX_FEC_CONFIG 11.4.2. DPRX_FEC_ERROR_COUNT
11.5. 128B/132B Link Quality Test Pattern Registers x
11.5.1. DPRX_BER_TEST_PATTERN
11.6. Sink MSA Registers x
11.6.1. DPRX0_MSA_MVID 11.6.2. DPRX0_MSA_NVID 11.6.3. DPRX0_MSA_HTOTAL 11.6.4. DPRX0_MSA_VTOTAL 11.6.5. DPRX0_MSA_HSP 11.6.6. DPRX0_MSA_HSW 11.6.7. DPRX0_MSA_HSTART 11.6.8. DPRX0_MSA_VSTART 11.6.9. DPRX0_MSA_VSP 11.6.10. DPRX0_MSA_VSW 11.6.11. DPRX0_MSA_HWIDTH 11.6.12. DPRX0_MSA_VHEIGHT 11.6.13. DPRX0_MSA_MISC0 11.6.14. DPRX0_MSA_MISC1 11.6.15. DPRX0_MSA_COLOR 11.6.16. DPRX0_VBID
11.7. Sink Audio Registers x
11.7.1. DPRX0_AUD_MAUD 11.7.2. DPRX0_AUD_NAUD 11.7.3. DPRX0_AUD_AIF0 11.7.4. DPRX0_AUD_AIF1 11.7.5. DPRX0_AUD_AIF2 11.7.6. DPRX0_AUD_AIF3 11.7.7. DPRX0_AUD_AIF4
11.8. Sink MST Registers x
11.8.1. DPRX_MST_VCPTAB0 11.8.2. DPRX_MST_VCPTAB1 11.8.3. DPRX_MST_VCPTAB2 11.8.4. DPRX_MST_VCPTAB3 11.8.5. DPRX_MST_VCPTAB4 11.8.6. DPRX_MST_VCPTAB5 11.8.7. DPRX_MST_VCPTAB6 11.8.8. DPRX_MST_VCPTAB7
11.9. Sink AUX Controller Interface x
11.9.1. DPRX_AUX_CONTROL 11.9.2. DPRX_AUX_STATUS 11.9.3. DPRX_AUX_COMMAND 11.9.4. DPRX_AUX_BYTE0 11.9.5. DPRX_AUX_BYTE1 11.9.6. DPRX_AUX_BYTE2 11.9.7. DPRX_AUX_BYTE3 11.9.8. DPRX_AUX_BYTE4 11.9.9. DPRX_AUX_BYTE5 11.9.10. DPRX_AUX_BYTE6 11.9.11. DPRX_AUX_BYTE7 11.9.12. DPRX_AUX_BYTE8 11.9.13. DPRX_AUX_BYTE9 11.9.14. DPRX_AUX_BYTE10 11.9.15. DPRX_AUX_BYTE11 11.9.16. DPRX_AUX_BYTE12 11.9.17. DPRX_AUX_BYTE13 11.9.18. DPRX_AUX_BYTE14 11.9.19. DPRX_AUX_BYTE15 11.9.20. DPRX_AUX_BYTE16 11.9.21. DPRX_AUX_BYTE17 11.9.22. DPRX_AUX_BYTE18 11.9.23. DPRX_AUX_I2C0 11.9.24. DPRX_AUX_I2C1 11.9.25. DPRX_AUX_RESET 11.9.26. DPRX_AUX_HPD
11.12. Sink CV2AXI Registers x
11.12.1. Sink CV2AXI Registers Summary 11.12.2. Sink CV2AXI Registers Description
11.12.2. Sink CV2AXI Registers Description x
11.12.2.1. STATUS (0x50) 11.12.2.2. ACTIVE SAMPLE COUNT (0x52) 11.12.2.3. F0_ACTIVE_LINE_COUNT (0x53) 11.12.2.4. F1_ACTIVE_LINE_COUNT (0x54) 11.12.2.5. TOTAL_SAMPLE_COUNT (0x55) 11.12.2.6. F0_TOTAL_LINE_COUNT (0x56) 11.12.2.7. F1_TOTAL_LINE_COUNT (0x57) 11.12.2.8. COLOR_PATTERN (0x5C) 11.12.2.9. CONTROL (0x64)
1. DisplayPort Intel® FPGA IP Quick Reference
2. About This IP
3. Getting Started
4. DisplayPort Intel® FPGA IP Hardware Design Examples
5. DisplayPort Source
6. DisplayPort Sink
7. DisplayPort Intel® FPGA IP Parameters
8. DisplayPort Intel® FPGA IP Simulation Example
9. DisplayPort API Reference
10. DisplayPort Source Register Map and DPCD Locations
11. DisplayPort Sink Register Map and DPCD Locations
12. DisplayPort Intel® FPGA IP User Guide Archives
13. Document Revision History for the DisplayPort Intel® FPGA IP User Guide

2.4. Performance and Resource Utilization

The resource utilization data indicates typical expected performance for the DisplayPort Intel® FPGA IP.

The following table lists the resources and expected performance for selected variations.

  • Intel® Arria® 10 (10AX115S2F45I1SG)
  • Intel® Cyclone® 10 GX (10CX220YF780E5G)
  • Intel® Stratix® 10 (1SG280HU1F50E2VGS1)
  • Intel® Agilex™ F-tile (AGIB027R31B1E2VR0)
Table 7.  DisplayPort 1.4 Intel® FPGA IP Resource Utilization The table below shows the resource information for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices using M20K. The resources were obtained using the following parameter settings:
  • Mode = simplex
  • Maximum lane count = 4 lanes
  • Maximum video input color depth = 8 bits per color (bpc)
  • Pixel input mode = 1 pixel per clock
Device Streams Direction Symbol per Clock ALMs Logic Registers Memory
Primary Secondary Bits M10K or M20K
Intel® Stratix® 10 SST (Single Stream) RX Dual 5,200 7,700 640 16,256 11
Quad 7,100 9,500 880 18,816 14
TX Dual 5,100 7,100 420 12,176 15
Quad 7,100 9,200 550 22,688 29

Intel® Arria® 10

SST (Single Stream) RX Dual 4,200 6,900 1,200 16,256 11
Quad 6,000 8,800 1,600 18,816 14
TX Dual 4,700 6,300 1,000 6,728 6
Quad 6,700 8,400 1,200 16,520 13
MST

(4 Streams)

 RX Quad 20,100 24,400 4,500 58,368 32
TX Quad 26,400 29,000 4,300 21,728 34
Intel® Cyclone® 10 GX SST (Single Stream) RX Dual 4,200 7,000 1,200 16,256 11
Quad 6,000 8,800 1,600 18,816 14
TX Dual 4,600 6,200 1,000 10,568 8
Quad 6,800 8,400 1,200 17,096 13
MST

(4 Streams)

 RX Dual 22,000 24,400 4,400

58,368

 32
TX Quad 26,500 29,000 4,400 36,576 32
Table 8.  DisplayPort 2.0 Intel® FPGA IP Resource UtilizationThe table below shows the resource information for Intel® Stratix® 10 devices using the M20K. The resource count for the DP2.0 includes the resource count for the DP1.4 as well (listed in Table 7). The resources were obtained using the following parameter settings:
  • Mode = simplex
  • Maximum lane count = 4 lanes
  • Maximum video input color depth = 8 bits per color (bpc)
  • Pixel input mode = 4 pixel per clock
Device Streams Direction ALMs Logic Registers Memory
Bits M10K or M20K
Intel® Stratix® 10 MST (1 Stream) RX 21,500 38,000 244,352 74
TX 32,500 43,000 265,232 154
MST (4 Streams) RX 48,000 70,751 357,632 164
TX 104,000 125,478 535,808 572
Table 9.  Intel Agilex FPGA IP Resource UtilizationThe table below shows the resource information for Intel® Agilex™ devices using M20K. The resources were obtained using the following parameter settings:
  • Mode = simplex
  • Maximum lane count = 4 lanes
  • Maximum video input color depth = 8 bits per color (bpc)
  • Pixel input mode = 4 pixel per clock
Device Stream Direction Symbols per Clock ALMs Logic Registers Memory
Bits M20k
Agilex SST RX Quad 7040 11781 18368 18
TX 7600 10149 26576 29
Table 10.  HDCP Resource UtilizationThe table lists the HDCP resource data for DisplayPort Intel® FPGA IP with configurations of SST (single stream) and at maximum lane of 4 configuration for Intel® Arria® 10 and Intel® Stratix® 10 devices.
Device HDCP IP Support HDCP Key Management Symbols per Clock ALMs Combinatorial ALUTs Registers M20K DSP
Intel® Arria® 10 HDCP 2.3 TX 0 Dual

6,752

10,724

13,138

10

3
Quad

9,934

16,760

16,716

10

3
1 Dual 7,165 11,350 13,615 12 3
Quad 10,374 17,364 17,561 12 3
HDCP 2.3 RX 0 Dual

7,395

11,721

13,775

11

3
Quad

10,547

17,674

17,335

11

3
1 Dual 7,785 12,420 14,213 13 3
Quad 10,972 18,424 18,167 13 3
HDCP 1.3 TX 0 Dual

2,505

3,826

5,336

2

0
Quad

3,724

5,648

5,882

2

0
1 Dual 2,849 4,429 5,846 4 0
Quad 4,142 6,335 6,635 4 0
HDCP 1.3 RX 0 Dual

1,995

2,879

4,248

3

0
Quad

3,270

4,810

4,851

3

0
1 Dual 2,382 3,549 4,821 5 0
Quad 3,677 5,472 5,604 5 0
Intel® Stratix® 10 HDCP 2.3 TX 0 Dual

7,723

11,555

13,685

10

3
Quad

10,767

17,154

17,842

10

3
1 Dual 8,232 12,376 14,123 12 3
Quad 11,082 17,741 18,125 12 3
HDCP 2.3 RX 0 Dual

8,431

12,626

14,647

11

3
Quad

11,304

18,071

18,586

11

3
1 Dual 8,796 13,174 14,707 13 3
Quad 11,690 18,658 18,847 13 3
HDCP 1.3 TX 0 Dual

3,154

4,108

5,181

2

0
Quad

4,794

6,194

7,640

2

0
1 Dual 3,614 4,894 5,916 4 0
Quad 5,169 6,979 6,791 4 0
HDCP 1.3 RX 0 Dual

2,602

3,355

4,245

3

0
Quad

4,229

5,428

6,452

3

0
1 Dual 3,045 4,022 4,904 5 0
Quad 4,656 6,173 5,773 5 0
Related Information
Level Two Title