DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 4/29/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

10.2.7. DPTX0_MSA_HSTART

Address: 0x0026

Direction: RO

Reset: 0x00000000

Note: This register is RO if TX_VIDEO_IM_ENABLE = 0 and RW if TX_VIDEO_IM_ENABLE = 1.
Table 71.  DPTX0_MSA_HSTART Bits

Bit

Bit Name

Function

31:16

Unused

15:0

HSTART

Main stream attribute HSTART