DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 11/12/2021
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10.5. Source CRC Registers

The CRC registers are allocated at addresses:

  • 0x0030 through 0x0032 for Stream 0
  • 0x0050 through 0x0052 for Stream 1
  • 0x0070 through 0x0072 for Stream 2
  • 0x0090 through 0x0092 for Stream 3
Note: Only registers for Stream 0 are listed in the following sections.

DPTX0_CRC_R

Address: 0x0030

Direction: RO

Reset: 0x00000000

Table 86.  DPTX0_CRC_R Bits

Bit

Bit Name

Function

31:16

Unused

15:0

CRC_R

Input video CRC for the red component

DPTX0_CRC_G

Address: 0x0031

Direction: RO

Reset: 0x00000000

Table 87.  DPTX0_CRC_G Bits

Bit

Bit Name

Function

31:16

Unused

15:0

CRC_G

Input video CRC for the green component

DPTX0_CRC_B

Address: 0x0032

Direction: RO

Reset: 0x00000000

Table 88.  DPTX0_CRC_B Bits

Bit

Bit Name

Function

31:16

Unused

15:0

CRC_B

Input video CRC for the blue component