DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 11/12/2021
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11.8. Sink CRC Registers

The CRC registers are available only Stream 0 and Stream 1 when the core is instantiated with parameter RX_SUPPORT_AUTOMATED_TEST = 1

DPRX0_CRC_R

Address: 0x0120

Direction: RO

Reset: 0x00000000

Table 191.  DPRX0_CRC_R Bits

Bit

Bit Name

Function

31:16

Unused

15:0

CRC_R

Output video CRC for the red component

DPRX0_CRC_G

Address: 0x0121

Direction: RO

Reset: 0x00000000

Table 192.  DPRX0_CRC_G Bits

Bit

Bit Name

Function

31:16

Unused

15:0

CRC_G

Output video CRC for the green component

DPRX0_CRC_B

Address: 0x0122

Direction: RO

Reset: 0x00000000

Table 193.  DPRX0_CRC_B Bits

Bit

Bit Name

Function

31:16

Unused

15:0

CRC_B

Output video CRC for the blue component