DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 11/12/2021
Public

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11.7.1. DPRX_AUX_CONTROL

For transaction requests:

  1. Wait for MSG_READY (in register DPRX_AUX_STATUS) to be 1, or enable the interrupt with AUX_IRQ_EN and wait for the interrupt request.
  2. Read the transaction request total length from LENGTH.
  3. Read the transaction request command from DPRX_AUX_COMMAND. This step also clears MSG_READY and LENGTH.
  4. Read the transaction request data payload from registers DPRX_AUX_BYTE0 to DPRX_AUX_BYTE15 (read LENGTH - 1 bytes).

For transaction replies:

  1. Wait for READY_TO_TX (in register DPRX_AUX_STATUS) to be 1. Implement a timeout (approximately 10 ms) counter.
  2. Write registers DPRX_AUX_COMMAND to DPRX_AUX_BYTE18 with transaction command and data payload.
  3. Write LENGTH with the transaction total message length (1 to 17, 1 for the command plus 1 to 16 for the data payload) and set TX_STROBE to 1. This sequence starts the reply transmission.

The sink asserts the IRQ when AUX_IRQ_EN = 1 and MSG_READY = 1. To deassert IRQ, set AUX_IRQ_EN to 0 or read from DPRX_AUX_COMMAND.

Address: 0x0100

Direction: RW

Reset: 0x00000000

Table 165.  DPRX_AUX_CONTROL Bits

Bit

Bit Name

Function

31

MSG_READY

0 = Waiting for a request

1 = A request has been completely received

30

READY_TO_TX

0 = Busy sending a reply or request waiting

1 = Ready to send a reply

29:9

Unused

8

AUX_IRQ_EN

Issues an IRQ to Nios II processor when the sink receives an AUX channel transaction from the source.

0 = Disable

1 = Enable

7

TX_STROBE

Writing this bit at 1 starts a reply transmission. Always read this bit as 0.

6:5

Unused

4:0

LENGTH

For the next transaction reply, total length of message to be transmitted (1 – 17), for the last received transaction request, total length of message received (1 – 17).