DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 11/12/2021
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2.4. Performance and Resource Utilization

The resource utilization data indicates typical expected performance for the DisplayPort Intel® FPGA IP.

The following table lists the resources and expected performance for selected variations. The results were obtained using the Intel® Quartus® Prime Pro Edition software version 20.2 for the following devices:

  • Intel® Arria® 10 (10AX115S2F45I1SG)
  • Intel® Cyclone® 10 GX (10CX220YF780E5G)
  • Intel® Stratix® 10 (1SG280HU1F50E2VGS1)
Table 7.   DisplayPort Intel® FPGA IP Resource Utilization The table below shows the resource information for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices using M20K. The resources were obtained using the following parameter settings:
  • Mode = simplex
  • Maximum lane count = 4 lanes
  • Maximum video input color depth = 8 bits per color (bpc)
  • Pixel input mode = 1 pixel per clock
Device Streams Direction Symbol per Clock ALMs Logic Registers Memory
Primary Secondary Bits M10K or M20K
Intel® Stratix® 10 SST (Single Stream) RX Dual 5,200 7,700 640 16,256 11
Quad 7,100 9,500 880 18,816 14
TX Dual 5,100 7,100 420 12,176 15
Quad 7,100 9,200 550 22,688 29

Intel® Arria® 10

SST (Single Stream) RX Dual 4,200 6,900 1,200 16,256 11
Quad 6,000 8,800 1,600 18,816 14
TX Dual 4,700 6,300 1,000 6,728 6
Quad 6,700 8,400 1,200 16,520 13
MST

(4 Streams)

RX Quad 20,100 24,400 4,500 58,368 32
TX Quad 26,400 29,000 4,300 21,728 34
Intel® Cyclone® 10 GX SST (Single Stream) RX Dual 4,200 7,000 1,200 16,256 11
Quad 6,000 8,800 1,600 18,816 14
TX Dual 4,600 6,200 1,000 10,568 8
Quad 6,800 8,400 1,200 17,096 13
MST

(4 Streams)

RX Dual 22,000 24,400 4,400

58,368

32
TX Quad 26,500 29,000 4,400 36,576 32
Table 8.  HDCP Resource UtilizationThe table lists the HDCP resource data for DisplayPort Intel® FPGA IP with configurations of SST (single stream) and at maximum lane of 4 configuration for Intel® Arria® 10 and Intel® Stratix® 10 devices.
Device HDCP IP Support HDCP Key Management Symbols per Clock ALMs Combinatorial ALUTs Registers M20K DSP
Intel® Arria® 10 HDCP 2.3 TX 0 Dual

6,752

10,724

13,138

10

3

Quad

9,934

16,760

16,716

10

3

1 Dual 7,165 11,350 13,615 12 3
Quad 10,374 17,364 17,561 12 3
HDCP 2.3 RX 0 Dual

7,395

11,721

13,775

11

3

Quad

10,547

17,674

17,335

11

3

1 Dual 7,785 12,420 14,213 13 3
Quad 10,972 18,424 18,167 13 3
HDCP 1.3 TX 0 Dual

2,505

3,826

5,336

2

0

Quad

3,724

5,648

5,882

2

0

1 Dual 2,849 4,429 5,846 4 0
Quad 4,142 6,335 6,635 4 0
HDCP 1.3 RX 0 Dual

1,995

2,879

4,248

3

0

Quad

3,270

4,810

4,851

3

0

1 Dual 2,382 3,549 4,821 5 0
Quad 3,677 5,472 5,604 5 0
Intel® Stratix® 10 HDCP 2.3 TX 0 Dual

7,723

11,555

13,685

10

3

Quad

10,767

17,154

17,842

10

3

1 Dual 8,232 12,376 14,123 12 3
Quad 11,082 17,741 18,125 12 3
HDCP 2.3 RX 0 Dual

8,431

12,626

14,647

11

3

Quad

11,304

18,071

18,586

11

3

1 Dual 8,796 13,174 14,707 13 3
Quad 11,690 18,658 18,847 13 3
HDCP 1.3 TX 0 Dual

3,154

4,108

5,181

2

0

Quad

4,794

6,194

7,640

2

0

1 Dual 3,614 4,894 5,916 4 0
Quad 5,169 6,979 6,791 4 0
HDCP 1.3 RX 0 Dual

2,602

3,355

4,245

3

0

Quad

4,229

5,428

6,452

3

0

1 Dual 3,045 4,022 4,904 5 0
Quad 4,656 6,173 5,773 5 0