DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 11/12/2021
Public

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11.6. Sink MST Registers

MST controller control.

Address: 0x00a0

Direction: RW

Reset: 0x00000000

Table 155.  DPRX_MST_CONTROL1 Bits

Bit

Bit Name

Function

31 VCPTAB_UPD_FORCE

This flag always reads back at 0.

1 = Force VC payload ID table update.

30 VCPTAB_UPD_REQ
  • 1 = Request for VC payload ID table update
  • 0 = No change to VC payload ID table
29:20 Unused  
19:16 VCP_ID3

VC payload ID for Stream 3

15:12 VCP_ID2

VC payload ID for Stream 2

11:8 VCP_ID1

VC payload ID for Stream 1

7:4 VCP_ID0

VC payload ID for Stream 0

3:1 Unused  
0 MST_EN

Enable or disable MST

  • 1 =MST framing
  • 0 = SST framing

When you assert VCPTAB_UPD_FORCE, the sink forces the VC payload table contained in DPRX_MST_VCPTAB0 through DPRX_MST_VCPTAB7 to be taken immediately into use.

When you assert VCPTAB_UPD_REQ, the sink requests the VC payload table contained in DPRX_MST_VCPTAB0 to DPRX_MST_VCPTAB7 to be taken into use after the next ACT sequence is detected.

The VC Payload ID values (1–15) used for VCP_ID0 to VCP_ID3 are different from those used by the DisplayPort source (1–63). The GPU must remap these values. The values used have to match those in the VC Payload ID table—DPRX_MST_VCPTAB0 to DPRX_MST_VCPTAB7 registers.

MST controller status

Address: 0x00a1

Direction: RO

Reset: 0x00000000

Table 156.  DPRX_MST_STATUS1 Bits

Bit

Bit Name

Function

31 Unused  
30 VCPTAB_ACT_ACK
  • 1 = ACT sequence detected and VC payload updated
  • 0 = No change to VC payload ID table
29:0 Unused  

VCPTAB_ACT_ACK resets to 0 when VCPTAB_UPD_REQ deasserted. VCPTAB_ACT_ACK is set to 1 if VCPTAB_UPD_REQ is asserted and the ACT sequence is detected, signaling that the table contained in DPRX_MST_VCPTAB0 to DPRX_MST_VCPTAB7 registers have been taken into use.