DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 11/12/2021
Public

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10.6. Source Audio Registers

The Audio registers are allocated at addresses:

  • 0x0033 for Stream 0
  • 0x0053 for Stream 1
  • 0x0073 for Stream 2
  • 0x0093 for Stream 3
Note: Only registers for Stream 0 are listed in the following sections.
Address: 0x002f

Direction: RW

Reset: The maximum number of channels supported minus 1 (0x00000000 – 0x00000007)

Table 89.  DPTX0_AUD_CONTROL Bits

Bit

Bit Name

Function

31

SOFT_MUTE

1 = Audio is muted

0 = Audio is muted if tx_audio_mute is asserted

30:24

Unused

17:16

LFEBPL

Audio InfoFrame LFE playback level (LFEPBL, see CEA-861-E specification)

15:8

CA

Audio InfoFrame channel allocation (CA, see CEA-861-E specification)

7:4

LSV

Audio InfoFrame level shift value (LSV, see CEA-861-E specification)

3

DM_INH

Audio InfoFrame down mix inhibit flag (DM_INH, see CEA-861-E specification)

2:0

CH_COUNT

Channel count

000 = 1 channel

001 = 2 channels

...

111 = 8 channels