DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 11/12/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.1. Main Data Path

The main link data path consists of the video packetizer, video geometry measurement, audio and secondary stream encoder, and training and link quality patterns generator.

The IP multiplexes data from these four paths and transmits it through a scrambler and an 8B/10B encoder. All the symbols, both those transmitted during video display period and those transmitted during video blanking period, are skewed by two Link symbol period between adjacent lanes.