DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 11/12/2021
Public

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6. DisplayPort Sink

The DisplayPort sink consists of a DisplayPort decoder block, a transceiver management block, a controller interface block, and an HDCP interface block with an Avalon® memory-mapped interface for connecting with an embedded controller such as the Nios II processor.

Figure 25. DisplayPort Sink Top-Level Block Diagram
Figure 26. DisplayPort Sink Functional Block Diagram
  

The device transceiver sends 20-bit (dual symbol) or 40-bit (quad symbol) parallel DisplayPort data to the sink. Each data lane is clocked in to the IP by its own respective clock output from the transceiver. Inside the sink, the four independent clock domains are synchronized to the lane 0 clock. Then, the IP performs the following actions:

  1. The IP aligns the data stream and performs 8B/10B decoding.
  2. The IP deskews the data and then descrambles it.
  3. The IP splits the unscrambled data stream into parallel paths.
    1. The SS decoder block performs secondary stream decoding, which the core transfers into the rx_ss_clk domain through a DCFIFO.
    2. The main data path extracts all pixel data from the incoming stream. Then, the gearbox block resamples the pixel data into the current bit-per-pixel data width. Next, the IP core crosses the pixel data into the rxN_vid_clk domain through a DCFIFO. Finally, the IP steers the data into a single, dual, or quad pixel data stream.
    3. MSA decode path.
    4. Video decode path.

You configure the sink to output the video data as a proprietary data stream. You specify the output pixel data width at 6, 8, 10, 12, or 16 bpc. This format can interface with downstream Video and Image Processing (VIP) Suite components.

The AUX controller can operate in an autonomous mode in which the sink controls all AUX channel activity without an external embedded controller. The IP outputs an AUX debugging stream so that you can inspect the activity on the AUX channel in real time.