DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 11/12/2021

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Document Table of Contents

6.5.2. AUX Interface

The IP has three ports to control the serial data across the AUX channel:

  • Data input (rx_aux_in)
  • Data output (rx_aux_out)
  • Output enable (rx_aux_oe). The output enable port controls the direction of data across the bidirectional link.

A state machine decodes the incoming AUX channel’s Manchester encoded data using the 16 MHz clock. The message parsing drives the state machine input directly. The state machine performs all lane training and EDID link-layer services.

The sink’s AUX interface also generates appropriate HPD IRQ events. These events occur if the sink’s main link decoder detects a signal loss.

The sink core uses the rx_cable_detect signal to detect when a source (upstream) device is physically connected and the rx_pwr_detect signal to detect when a source device is powered. The sink core keeps the rx_hpd signal deasserted if both the rx_cable_detect and rx_pwr_detect signals are not asserted.