DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 11/12/2021
Public

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10.2.11. DPTX0_MSA_HWIDTH

Address: 0x002a

Direction: RO

Reset: 0x00000000

Note: This register is RO if TX_VIDEO_IM_ENABLE = 0 and RW if TX_VIDEO_IM_ENABLE = 1.
Table 71.  DPTX0_MSA_HWIDTH Bits

Bit

Bit Name

Function

31:16

Unused

15:0

HWIDTH

Main stream attribute HWIDTH