DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 11/12/2021
Public

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6.5.6. RX Transceiver Interface

The transceiver or Native PHY IP core instance is no longer instantiated within the DisplayPort Intel® FPGA IP. The DisplayPort Intel® FPGA IP uses a soft 8B/10B decoder. This interface receives RX transceiver recovered data (rx_parallel_data) in either dual symbol (20-bit) or quad symbol (40-bit) mode, and drives the digital reset (rx_digitalreset), analog reset (rx_analogreset), and controls the CDR circuitry locking mode.