DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 11/12/2021
Public

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11.1.3. DPRX_BER_CONTROL

Address: 0x0002

Direction: CRW

Reset: 0x00000000

Note: When PHY_SINK_TEST_LANE_EN equals 1, CR_LOCK and SYM_LOCK bits (register DPRX_RX_STATUS) are forced to 1 for lanes that are not being tested.
Table 126.  DPRX_BER_CONTROL Bits

Bit

Bit Name

Function

31:28

Unused

27 RSTI3

Writing this bit at 1 resets lane 3 bit-error counter in register DPRX_BER_CNTI1. Always reads as ‘0’.

26 RSTI2

Writing this bit at 1 resets lane 2 bit-error counter in register DPRX_BER_CNTI1. Always reads as ‘0’.

25 RSTI1

Writing this bit at 1 resets lane 1 bit-error counter in register DPRX_BER_CNTI0. Always reads as ‘0’.

24 RSTI0

Writing this bit at 1 resets lane 0 bit-error counter in register DPRX_BER_CNTI0. Always reads as ‘0’.

23

Unused

 
22:21 PHY_SINK_TEST_LANE_SEL

Specifies the lane that is being tested, when PHY_SINK_TEST_LANE_EN is 1,

  • 00 = Lane 0
  • 01 = Lane 1
  • 10 = Lane 2
  • 11 = Lane 3
20 PHY_SINK_TEST_LANE_EN Writing this bit at 1 enables single lane PHY test, Write 0 to disable single lane PHY test.

19

RST3

Writing this bit at 1 resets the lane 3 bit-error counter in register DPRX_BER_CNT1. Always reads as 0.

18

RST2

Writing this bit at 1 resets the lane 2 bit-error counter in register DPRX_BER_CNT1. Always reads as 0.

17

RST1

Writing this bit at 1 resets lane 1 bit-error counter in register DPRX_BER_CNT0. Always reads as 0.

16

RST0

Writing this bit at 1 resets lane 0 bit-error counter in register DPRX_BER_CNT0. Always reads as 0.

15:14

Unused

13:11

PATT3

Pattern selection for lane 3:

  • 000 = No test pattern (normal mode)
  • 011 = PRBS7
  • 101 = HBR2Compliance EYE pattern

10:8

PATT2

Pattern selection for lane 2:

  • 000 = No test pattern (normal mode)
  • 011 = PRBS7
  • 101 = HBR2 Compliance EYE pattern

7:5

PATT1

Pattern selection for lane 1:

  • 000 = No test pattern (normal mode)
  • 011 = PRBS7
  • 101 = HBR2 Compliance EYE pattern

4:2

PATT0

Pattern selection for lane 0:

  • 000 = No test pattern (normal mode)
  • 011 = PRBS7
  • 101 = HBR2 Compliance EYE pattern

1:0

CNTSEL

Count selection:

  • 00 = Disparity and code error counts
  • 01 = Disparity error counts
  • 10 = Code error counts
  • 11 = Reserved