DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 11/12/2021

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6.5.8. Secondary Stream Interface

The secondary streams data can be received through the rxN_ss interfaces. The interfaces do not allow for back-pressure and assume the downstream logic can handle complete packets. The rxN_ss interface does not distinguish between the types of packets it receives.

Note: The DisplayPort Intel® FPGA IP supports InfoFrame SDP versions 1.2 and 1.3 over the Main-Link. INFOFRAME SDP version 1.2 shall be used to convey Audio INFOFRAME control information, as specified in CEA-861-F and CEA-861.2. Other INFOFRAME coding types, as specified in CEA-861-F, Table 5, and CEA-861.3, shall use INFOFRAME SDP version 1.3. Refer to the VESA DisplayPort Standard version 1.2a, Section for detailed definition.

The format of the rxN_ss interface output corresponds to four 15-nibble code words as specified by the VESA DisplayPort Standard version 1.2a, Section These 15-nibble code words are typically supplied to the downstream Reed-Solomon decoder. The format differs for both header and payload, as shown in the following figure.

Figure 32. rxN_ss Input Data Format

The following figure shows a typical secondary stream packet with the four byte header (HB0, HB1, HB2, and HB3) and 32-byte payload (DB0, ..., DB31). Each symbol has an associated parity nibble (PB0, ..., PB11). Downstream logic uses start-of-packet and end-of-packet to determine if the current input is a header or payload symbol.

Data is clocked out of the rxN_ss port using the rx_ss_clk signal. This signal is the same phase and frequency as the main link lane 0 clock.

Figure 33. Typical Secondary Stream Packet