DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 11/12/2021
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10.2.5. DPTX0_MSA_HSP

Address: 0x0024

Direction: RO

Reset: 0x00000000

Note: This register is RO if TX_VIDEO_IM_ENABLE = 0 and RW if TX_VIDEO_IM_ENABLE = 1.
Table 65.  DPTX0_MSA_HSP Bits

Bit

Bit Name

Function

31:1

Unused

0

HSP

Main stream attribute horizontal sync polarity:

  • 0 = Positive
  • 1 = Negative