External Memory Interfaces Agilex™ 7 F-Series and I-Series FPGA IP User Guide

ID 683216
Date 3/29/2024
Document Table of Contents

9.3. SPICE Decks

The generated EMIF IP provides three SPICE decks for channel evaluation: address/command channel, FPGA write operation, and FPGA read operation.

Each simulation deck uses a 12-line channel model that maps to a 12-pin lane within a sub-bank. In all decks, two pins are designated as clock or strobe pins, one pin is designated as a victim pin and driven with a PRBS-10 pattern, and the remaining pins are designated as aggressor pins and driven with identical PRBS-15 patterns.