External Memory Interfaces Agilex™ 7 F-Series and I-Series FPGA IP User Guide

ID 683216
Date 3/29/2024
Document Table of Contents

9. Agilex™ 7 F-Series and I-Series FPGA EMIF IP – I/O Timing Closure

This chapter describes how to evaluate I/O timing outside of the FPGA, by determining whether the memory interface channel of your printed circuit board (PCB) meets the necessary signal integrity requirements for your design.

This approach is based on SPICE analog simulations using extracted models of the PCB channel, IBIS models of the FPGA buffers, and IBIS models of the memory devices to determine if the external I/O channel is adequate for the target design.