External Memory Interfaces Agilex™ 7 F-Series and I-Series FPGA IP User Guide

ID 683216
Date 3/29/2024
Document Table of Contents

11.10.1. Enabling the On-Chip Debug Port

To export the cal_debug port, set the Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port parameter to Export, when parameterizing the emif_cal IP.
Figure 254. Enabling the On-Chip Debug Port
You may then create your own logic to perform the desired read/write commands on the cal_debug Avalon® memory-mapped interface.
Figure 255. Connecting Your Own Logic