External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP User Guide

ID 683216
Date 6/26/2023
Public
Document Table of Contents
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4.4.7. caltiming2

address=33(32 bit)

Field Bit High Bit Low Description Access
cfg_t_param_rd_to_wr_diff_bg 5 0 Read to write command timing on different bank groups. Read
cfg_t_param_rd_to_pch 11 6 Read to precharge command timing. Read
cfg_t_param_rd_ap_to_valid 17 12 Read command with autoprecharge to data valid timing. Read
cfg_t_param_wr_to_wr 23 18 Write to write command timing on same bank. Read
cfg_t_param_wr_to_wr_diff_chip 29 24 Write to write command timing on different chips. Read