External Memory Interfaces Agilex™ 7 F-Series and I-Series FPGA IP User Guide

ID 683216
Date 3/29/2024
Document Table of Contents QDR-IV Read Calibration

DQSen Calibration

The calibration algorithm does not use a hardware state machine; rather, it calibrates cycle-level delays using software, and subcycle delays using DQS tracking hardware. The algorithm requires good data in memory, and therefore relies on guaranteed writes. The algorithm enables DQS tracking to calibrate the phase component of DQS enable, and then issues a guaranteed write, followed by back-to-back reads. The algorithm sweeps DQSen values cycle by cycle until the read operation succeeds. Because the DQSen calibration occurs before Read Deskew, only one successful data bit is required to register a pass. The algorithm staggers the read DQ bus to ensure that at least one DQ bit falls within the valid Read window.The process then repeats for all other read groups.

Figure 73. Sweep DQSen at Cycle-Level Until At Least One DQ Bit is Passing
Figure 74. Staggering DQ Bus to Ensure at Least One Passing DQ bit

Deskew Calibration

Read deskew calibration occurs before write leveling, and must occur at least twice: once before write calibration using simple data patterns from guaranteed writes, and again after write calibration using complex data patterns.

To ensure that guaranteed writes work correctly, the Write Leveling Phase training occurs before the guaranteed writes. The goal of Write Leveling Phase training is to align the rising edge for write DQS with the rising edge of MEM_CLK at the DRAM.

Figure 75. Write Leveling Phase Training -Align Write DQS with MEM_CLK at DRAM

The algorithm uses the DRAM write leveling feature for Write Leveling Phase Training. In this mode the following actions occur:

  • The algorithm adjusts the DQS output delay (at the FPGA side) while toggling write DQS signal.
  • The DRAM samples the MEM_CLK using the rising edge of write DQS and outputs the sampled value on DQ pins.
  • The algorithm continues to adjust the DQS output while toggling the write_DQS signal until it detects a 0 to 1 transition on the DQ pins.
Figure 76. DQS and MEM_CLK are phase aligned when 0 to 1 transition is detected on DQ pins

In guaranteed writes, the algorithm writes a burst of 0s to one location and a burst of 1s to another location. The data from the back-to back reads from these two locations is used as a simple data pattern for read deskew calibration.

Figure 77. Guarantee Write – Writing a Simple Data Pattern to Memory

Before the write calibration, the deskew calibration algorithm performs a guaranteed write, and then sweeps dqs_in delay values from low to high, to find the right-hand edge of the read window. The algorithm then sweeps dq_in delay values from low to high, to find the left-hand edge of the read window. The algorithm then applies updated dqs_in and dq_in delay values to center the read window. The process then repeats for all data pins.

Figure 78. A Passing Back-to-back Read with Simple Data Pattern
Figure 79. Increase dqs_in Delay Until Read Fails -Right Edge is Identified
Figure 80. Increase dq_in Delay Until Read Fails-Left Edge is Identified
Figure 81. Centering the Read Window

After the write path is calibrated, the algorithm performs another read-deskew calibration using a complex data pattern.

Vref-in Calibration

Read Vref-in calibration begins by programming Vref-in with an arbitrary value. The algorithm then sweeps the Vref-in value from the starting value to both ends, and measures the read window for each value. The algorithm selects the Vref-in value which provides the maximum read window. Vref-in is generated from the VCCIO on the I/O banks used for DQ/DQS signals and calibrated internally in FPGA.

LFIFO Calibration

Read LFIFO calibration normalizes read delays between groups. The PHY must present all data to the controller as a single data bus. The LFIFO latency should be large enough for the slowest read data group, and large enough to allow proper synchronization across FIFOs.