External Memory Interfaces Agilex™ 7 F-Series and I-Series FPGA IP User Guide

ID 683216
Date 3/29/2024
Document Table of Contents Debugging VREFIN Calibration Failure

  1. Ensure that the VCCIO of the failing group is powered up to VCCIO=1.2V at the FPGA side.
  2. Regenerate the EMIF IP with other Initial VREFIN values. It defaults to 68% when using the default FPGA I/O settings.
    Figure 84. Changing the Initial VREFIN Value