External Memory Interfaces Agilex™ 7 F-Series and I-Series FPGA IP User Guide

ID 683216
Date 3/29/2024
Document Table of Contents

5.2.3. Functional Simulation with Verilog HDL

Simulation scripts for the Synopsys* and Siemens EDA simulators are provided for you to run the design example.

The simulation scripts are located in the following main folder locations:

Simulation scripts in the simulation folders are located as follows:

  • sim\ed_sim\mentor\msim_setup.tcl
  • sim\ed_sim\synopsys\vcs\vcs_setup.sh
  • sim\ed_sim\synopsys\vcsmx\vcsmx_setup.sh

For more information about simulating Verilog HDL or VHDL designs using command lines, refer to the Questa - Intel FPGA Edition, ModelSim, and QuestaSim Simulator Support chapter in the Quartus® Prime Pro Edition User Guide, Third-party Simulation.