External Memory Interfaces Agilex™ 7 F-Series and I-Series FPGA IP User Guide
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Ixiasoft
Visible to Intel only — GUID: rva1550858932217
Ixiasoft
6.4.2.2. PLL
For the clock source, use the clock input pin specifically dedicated to the PLL that you want to use with your external memory interface. The input and output pins are only fully compensated when you use the dedicated PLL clock input pin.
For specific pin connection requirements, refer to Specific Pin Connection Requirements .