External Memory Interfaces Agilex™ 7 F-Series and I-Series FPGA IP User Guide

ID 683216
Date 3/29/2024
Document Table of Contents Address and Command Signals

Confirm that address and command signals are reaching the memory devices correctly.

After the memory interface has been successfully calibrated, you can probe the ALERT_N pin to determine if any memory component has encountered an address and command parity error.