External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP User Guide

ID 683216
Date 6/26/2023
Public
Document Table of Contents
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4.4.12. sideband0

address=43(32 bit)

Field Bit High Bit Low Description Access
mr_cmd_trigger 0 0 When asserted, triggers the execution of the mode register command. Read/Write