Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

ID 683190
Date 7/15/2022
Document Table of Contents Verifying Timing Constraints are Satisfied

When the compile is complete, verify timing constraints are satisfied. You can verify this in the GUI using Timing Analyzer or you can review the generated report file in prj/pac_baseline/build/chip.sta.summary.

  1. Go to the $ cd prj/pac_baseline/build directory.
  2. Review chip.sta.summary for timing constraints with negative slack
  3. Create an unsigned FPGA image file for loading into flash. This instruction assumes the board root key has not been programmed.
    $ PACSign SR -t UPDATE -H openssl_manager -i pac-n3000-secure-update-raw.bin\ 
    -o unsigned_PAC_N3000_RSU.bin
    Load FPGA image:
    $ sudo fpgasupdate unsigned_PAC_N3000_RSU.bin  <N3000 PCIe B:D.F>
    >>Please note this command takes ~40 minutes to complete
    $ sudo rsu fpga <N3000 PCIe B:D.F>
    Load host application and run with FPGA:
    1. Change directory to software:
      $ cd hls_example/hw/hls_afu/sw 
      $ make
    2. Set hugepage:
      # echo 200 > /sys/kernel/mm/hugepages/hugepages-2048kB/nr_hugepages
    3. Run the application:
      $ sudo ./hls_afu_host

      Using Avalon Slave at offset 0x40. No vector size specified. Default to size 64 floats. run ./hls_afu_host <vectorsize> to specify a vector size at runtime using test vector of size 64.

    4. Running Test:
      AFU DFH REG = 1000010000000000
      AFU ID LO = 944028430b016f3d
      AFU ID HI = 5fa7fd4b867c484c
      AFU NEXT = 00000000
      AFU RESERVED = 00000000
      end of output memory before executing kernel:
          [62] - -6259853398707798016.000000 (0xdeadbeef)
          [63] - -6259853398707798016.000000 (0xdeadbeef)
          [64] - -6259853398707798016.000000 (0xdeadbeef)
          [65] - 0.000000 (0x0)
      Interrupt enabled = 00000000
      Interrupt enabled = 00000001
      AFU Latency: 0.04500 milliseconds
      Poll success. Return = 1
      check output memory:
      output memory OK!
      sum: Expected 715.000000, calculated 715.000000

      The FPGA writes a full 512-bit word (64 bytes) to host memory, so if the size of your test vector (in bytes) is not a multiple of 64, the FPGA will overwrite some space at the end of output memory. fpgaPrepareBuffer() allocates your host memory in a buffer that is a multiple of 64 bytes, so the FPGA behavior will not affect your application. You should expect to see a single 0xdeadbeef at the end of the output memory if and only if the size of your test vector (determined by vector_size, and the data type) is a multiple of 64 bytes (that is, if vector_size is a multiple of 16).