Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

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ID 683190
Date 7/15/2022
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Introduction 3. High Level Description 4. Creating an N3000 FPGA Design 5. Capturing Signals in AFU with Signal Tap 6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants
1. About This Document x
1.1. Acronym List
2. Introduction x
2.1. Base Knowledge and Skills Prerequisites
2.1. Base Knowledge and Skills Prerequisites x
2.1.1. Considerations
3. High Level Description x
3.1. Steps for Creating Your AFU 3.2. N3000 Block Diagram 3.3. Factory Image Description
3.2. N3000 Block Diagram x
3.2.1. In-Line Data Path 3.2.2. Supported Ethernet Network Configurations 3.2.3. Provided Files 3.2.4. Internal Interfaces
3.2.3. Provided Files x
3.2.3.1. Directory Structure
3.2.4. Internal Interfaces x
3.2.4.1. Core Cache Interface (CCI-P) 3.2.4.2. Ethernet Interface 3.2.4.3. Ethernet MAC 3.2.4.4. 40G – 25G Gearbox 3.2.4.5. External Memory Interfaces 3.2.4.6. Ethernet MAC Wrapper Register Access
3.2.4.1. Core Cache Interface (CCI-P) x
3.2.4.1.1. FPGA Internal Register Access
3.2.4.5. External Memory Interfaces x
3.2.4.5.1. DDR4A and DDR4B 3.2.4.5.2. DDR4C 3.2.4.5.3. QDR4 Interface
4. Creating an N3000 FPGA Design x
4.1. Create New Project Directory 4.2. Create Your AFU Design Files 4.3. Build with make 4.4. Check Timing 4.5. Loading Your AFU into the Intel FPGA PAC N3000
4.2. Create Your AFU Design Files x
4.2.1. ccip_std_afu.sv 4.2.2. AFU File 4.2.3. QSF File 4.2.4. SDC File
4.5. Loading Your AFU into the Intel FPGA PAC N3000 x
4.5.1. Loading Your FPGA Image with JTAG 4.5.2. AFU Clocks 4.5.3. Creating an AFU with High Level Synthesis (HLS)
4.5.1. Loading Your FPGA Image with JTAG x
4.5.1.1. Preparing Your N3000 for JTAG 4.5.1.2. Disabling PCIe* Automatic Error Reporting (AER) 4.5.1.3. Using JTAG to Load the Intel® Arria® 10 *.sof file 4.5.1.4. How to Rescan PCIe* Bus and Re-enable PCIe* AER
4.5.2. AFU Clocks x
4.5.2.1. Hello AFU Example (uClk_usr) 4.5.2.2. Hello AFU Example (pll)
4.5.3. Creating an AFU with High Level Synthesis (HLS) x
4.5.3.1. Setting Up a Shell for HLS Development Work 4.5.3.2. Using the Initial Shell Design as a Shell 4.5.3.3. Compiling the Design and Producing a new N3000 FPGA Bitstream 4.5.3.4. Verifying Timing Constraints are Satisfied
5. Capturing Signals in AFU with Signal Tap x
5.1. Adding Signal Tap to the Design 5.2. Loading FPGA Image 5.3. Set Up Connections 5.4. How to Exit from the Debug Session 5.5. Troubleshooting Remote Debug Connections
1. About This Document
2. Introduction
3. High Level Description
4. Creating an N3000 FPGA Design
5. Capturing Signals in AFU with Signal Tap
6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

4.5.1.1. Preparing Your N3000 for JTAG

  1. Remove the cover to the N3000 board by removing the screws and lifting off cover, as shown below:
    Figure 28.  N3000 with Cover Attached
    Figure 29.  N3000 Board Exposed
  2. Turn the N3000 board over to the backside and locate "SW2" as shown below:
    Figure 30. Bottom Side of the N3000 Board
    Note: The "SW2" Switch must be in the OFF position.

    You can tell the switch is set to OFF by using an Ohm meter to measure resistance across the switch. When the switch is set to OFF, the resistance should be approximately 10-13 K Ohms. Slide the switch using a probe tool to OFF if required.

  3. Use a 10 Position receptacle, as shown below, to extend the N3000 JTAG header for connectivity above the heatsink to the Intel® FPGA Download Cable II. Note: Pay attention to the manufacturer and part number.
    Figure 31. 10 Position Receptacle
  4. Attach the Intel® FPGA Download Cable II header as shown below:
    Figure 32.  Intel® FPGA Download Cable II Attached to the N3000
    Note: Notice the Intel® FPGA Download Cable II orientation as shown above. There is no keying of this connector.
  5. Turn OFF the power to the server and insert the N3000 card into a PCIe Gen3 X 16 slot.
  6. Attach the auxiliary 12 V connection to the N3000 card, as shown below:
    Figure 33. Auxiliary 12 V Connection
    CAUTION:
    Make absolutely certain substantial server air flow velocity is provided. The card will overheat if adequate airflow is not provided.
  7. Power on server.
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