Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

ID 683190
Date 7/15/2022
Public
Document Table of Contents

3.2.4.1.1. FPGA Internal Register Access

Access to internal FPGA registers with the PCIe* 0 CCI-P interface uses Memory Mapped I/O (MMIO) access. You may use the following types of internal registers:
  • Direct access
  • Indirect access

Direct access registers consist of MMIO addressable registers. The provided example design hello_afu.sv illustrates direct access registers.

The CCI-P protocol MMIO address space is limited to 256 kB. The indirect access registers provide a mechanism to address larger areas by including control and response registers for extended slave addressing. AFU designers may use the provided ccip_to_avmm module to provide indirect access for your Avalon® memory-mapped interface slave modules. The ccip_to_avmm module block diagram is shown below:
Figure 4. CCI-P to Avalon® memory-mapped interface Block
As can be seen in this block diagram, this module consists of the following:
  • ccip_async_shimCCI-P to and from Avalon® clock domain crossing
  • ccip_avmm_mmio – converts MMIO to and from Avalon® memory-mapped interface
  • bbs_regs_mm_wrap – contains CCI-P required DFH and AFU ID registers and indirect command and status registers
The indirect command and status registers are defined as follows:
Table 1.  Control Register
Field Name Range Access Description
cmd [63:62] RW

Command for slave:

0x0 – NOP

0x1 – indirect read request

0x2 – indirect write request

addr [61:32] RW Slave address
Write data [31:0] RW Slave write data
For an indirect write request:
  1. Write the following to the Control register:
    • cmd = 0x2
    • addr
    • Write data
  2. Poll on the RW valid field of the Status register for RW valid = 1 to verify that the write is successful.
For an indirect read request,:
  1. Write the following to the Control register::
    • cmd = 0x1
    • addr
  2. Poll on the RW valid field of the Status register for RW valid = 1 to verify that the RD Data field contains valid data.

BBS_regs_mm_wrap Access Behavior

The following figures show the bbs_regs_mm_wrap upstream Avalon® memory-mapped interface slave to downstream Avalon® memory-mapped interface slave waveforms for indirect write and read operations.

Note: Pay attention to the downstream Avalon® memory-mapped interface master waveforms for proper operation with your slave module.

Indirect Write and Read Requests with Non-Blocking Access

The back pressure signal (avmm_s_waitrequest) is not used from the indirect access module to the CCI-P; and a write (WR) or read (RD) transaction can start at any time, but must complete in the next clock cycle.

Figure 5 and Figure 6 demonstrate this behavior:
Figure 5.  Avalon® memory-mapped interface Waveforms for Indirect Write Request with NONBLOCKING_ACCESS_EN = 1
Figure 6.  Avalon® memory-mapped interface Waveforms of Indirect Read Request with NONBLOCKING_ACCESS_EN = 1

Write and Indirect Read Requests with Blocking Access

The back pressure signal (avmm_s_waitrequest) is always set to ‘1’ in the NOP state; and a write (WR) or read (RD) transaction can start when avmm_s_waitrequest = 1, but cannot finish until avmm_s_waitrequest != 0.

Figure 7 and Figure 8 demonstrate this behavior:
Figure 7. Write Request with NONBLOCKING_ACCESS_EN = 0
Figure 8. Waveform of Indirect Read Request with NONBLOCKING_ACCESS_EN = 0

Avalon® memory-mapped interface Master Response to a Read Request with Non-Blocking and Blocking Access

You can read data on the bus for the following conditions:
  • When AVMM_MASTER_READDATAVALID_EN = 1 and avmm_m_readdatavalid are valid
  • When AVMM_MASTER_READDATAVALID_EN = 0 and (!avmm_m_waitrequest & avmm_m_read) are valid
Figure 9 and Figure 10 demonstrate this behavior:
Figure 9.  Avalon® memory-mapped interface Master Response to a Read Request with NONBLOCKING_ACCESS_EN = 1
Figure 10.  Avalon® memory-mapped interface Master Response to a Read Request with NONBLOCKING_ACCESS_EN = 0